Datasheet

Electrical characteristics
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARY NXP Semiconductors66
4.10.4.1 SD3.1/eMMC5.1 High-Speed mode AC Timing
The following figure depicts the timing of SD3.1/eMMC5.1 High-Speed mode, and Table 57 lists the
timing characteristics.
Figure 27. SD3.1/eMMC5.1 High-Speed mode Timing
Table 57. SD3.1/eMMC5.1 High-Speed mode interface timing specification
ID Parameter Symbols Min Max Unit
Card Input Clock
SD1 Clock Frequency (Low Speed) f
PP
1
1
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
0400kHz
Clock Frequency (SD/SDIO Full Speed/High Speed) f
PP
2
2
In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0
25 MHz. In high-speed mode,
clock frequency can be any value between 0
50 MHz.
025/50MHz
Clock Frequency (MMC Full Speed/High Speed) f
PP
3
020/52MHz
Clock Frequency (Identification Mode) f
OD
100 400 kHz
SD2 Clock Low Time t
WL
7—ns
SD3 Clock High Time t
WH
7—ns
SD4 Clock Rise Time t
TLH
—3ns
SD5 Clock Fall Time t
THL
—3ns
eSDHC Output/Card Inputs SD_CMD, SD_DATA (Reference to SD_CLK)
SD6 eSDHC Output Delay t
OD
–6.6 3.6 ns
eSDHC Input/Card Outputs SD_CMD, SD_DATA (Reference to SD_CLK)
SD7 eSDHC Input Setup Time t
ISU
2.5 ns
SD8 eSDHC Input Hold Time
4
t
IH
1.5 ns
SD1
SD3
SD5
SD4
SD7
SDx_CLK
SD2
SD8
SD6
Output from uSDHC to card
Input from card to uSDHC
SDx_DATA[7:0]
SDx_DATA[7:0]