Datasheet

Electrical characteristics
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARYNXP Semiconductors 65
4.10.4
Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC)
AC
Timing
This section describes the electrical information of the uSDHC, including:
SD3.1/eMMC5.1 High-Speed mode AC Timing
eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode timing
HS400 AC timing—eMMC 5.1 only
HS200 Mode Timing
SDR50/SDR104 AC Timing
t8 FSR output delay 7
4
x ck
i ck a
ns
t9 RX data pins - setup requirement 2
10
—x ck
i ck
ns
t10 RX data pins - hold requirement 2
0
—x ck
i ck
ns
t11 FSR - setup requirement 2
10
—x ck
i ck a
ns
t12 FSR - hold requirement 2
0
—x ck
i ck a
ns
t13 Flags - setup requirement 2
10
—x ck
i ck s
ns
t14 Flags - hold requirement 2
0
—x ck
i ck s
ns
RX_HF_CLK / TX_HX_CLK clock cycle 20 ns
TX_HF_CLK input to SCKT 10 ns
RX_HF_CLK input to SCKR 10 ns
1
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode (SCKT and SCKR are two different clocks)
i ck s = internal clock, synchronous mode (SCKT and SCKR are the same clock)
Table 56. Enhanced Serial Audio Interface (ESAI) Timing (continued)
ID Parameters Min Max Condition
1
Unit