Datasheet
Electrical characteristics
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARYNXP Semiconductors 47
4.8.3.2 ECC for DDR3L
i.MX 8QuadXPlus/8DualXPlus supports up to 8-bit ECC when using DDR3L only. This is accomplished
through the use of a fifth byte lane (DQS4[P:N],DM4, DQ[32:39]). When using the fifth byte lane, it is
not a requirement that all DDR3L devices be identical, but it is required that all devices be able to operate
with the same timing parameters. This can be easily accomplished by using memory containing the same
die(s), but contained in different packages. Consult the DDR3L device datasheets for timing requirements.
The fifth byte lane is for the exclusive use of ECC. If not using ECC, leave the pins as not connected. For
LPDDR4 mode, pins DQS4[P:N],DM4, DQ[32:39] are not used and cannot be substituted for one of the
other byte lanes. If using LPDDR4 mode, leave these pins as not connected.
4.9 General-Purpose Media Interface (GPMI) Timing
The GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up to 400 MB/s
I/O speed, and individual chip select. It supports Asynchronous Timing mode, Source Synchronous
Timing mode, and Toggle Timing mode, as described in the following subsections.