Datasheet

Electrical characteristics
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARY NXP Semiconductors46
DDR_DM_4 DM_4
DDR_DCF00 A5 CA2_A
DDR_DCF01 A6 CA4_A
DDR_DCF03 A7 CA5_A
DDR_DCF04 A8
DDR_DCF05 A9
DDR_DCF07 RAS_N
DDR_DCF08 A3 CA3_A
DDR_DCF09 ODT0 ODT_CA_A
DDR_DCF10 A1 CS0_A
DDR_DCF11 A0 CA0_A
DDR_DCF12 A2 CS1_A
DDR_DCF14 CKE0_A
DDR_DCF15 CKE1_A
DDR_DCF16 A4 CA1_A
DDR_DCF17 A12 CA4_B
DDR_DCF18 RESET_N RESET_N
DDR_DCF19 A14 CA5_B
DDR_DCF20 A15
DDR_DCF21 BA0
DDR_DCF22 BA1
DDR_DCF23 BA2
DDR_DCF24 CAS_N
DDR_DCF25 ODT1 ODT_CA_B
DDR_DCF26 A13 CA3_B
DDR_DCF27 A10 CA0_B
DDR_DCF28 CS0_N CS0_B
DDR_DCF29 CS1_N CS1_B
DDR_DCF30 CKE0 CKE0_B
DDR_DCF31 CKE1 CKE1_B
DDR_DCF32 A11 CA1_B
DDR_DCF33 CA2_B
Table 44. Clock, data, and command address signals for LPDDR4 and DDR3L modes (continued)
Signal name
DDR3L LPDDR4