Datasheet
Introduction
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARY NXP Semiconductors4
I/O 1× PCIe 3.0 (1-lane) with L1 substate support
1× USBOTG 3.0 with PHY—USB 3.0 can be used as USB 2.0
1× USBOTG 2.0 (with PHY)
2× 1Gb Ethernet with AVB (can be used as 10/100 Mbps ENET with AVB)
3× CAN/CAN-FD
1× Media Local Bus (MLB25/50)
6× UARTs:
•4× UARTs (3× with hardware flow control)
•1× UART tightly coupled with Cortex-M4F cores
•1× SCU UART (Note: SCU UART is dedicated to the SCU and not available for
general use)
10× I
2
C (note that there are two types of I
2
C: High-speed I
2
C ports with DMA support,
and low-speed I
2
C ports with no DMA support, which are used in conjunction with a
specific PHY interface—for example, for touchscreen):
•4× I2C: High Speed, DMA support
•4× I2C: Low Speed, no DMA support
•1× I2C: PMIC control (dedicated)
•1× I2C: Cortex M4F (dedicated)
Note: I2C ports associated with a PHY (e.g. MIPI DSI) can be used generally but
require the PHY to be powered on even if the PHY interface itself is not used.
4× SAI (SAI0 and SAI1 are transmit/receive; SAI2 and SAI3 are receive only)
1× Enhanced Serial Audio Interface (ESAI)
2× ASRC (Asynchronous Sample Rate Converter) (note: no I/O signals are directly
connected to this module)
1× SPDIF (Tx and Rx)
1× 6-channel ADC converter
3.3 V/1.8 V GPIO
4× PWM channels
1× 6×8 KPP (Key Pad Port)
1× MQS (Medium Quality Sound)
4× SPI
Packaging Case FCPBGA 21 x 21 mm, 0.8 mm pitch
Case FCPBGA 17 x 17 mm, 0.8 mm pitch
Table 1. i.MX 8QuadXPlus/8DualXPlus advanced features (continued)
Function Feature