Datasheet
Electrical characteristics
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARYNXP Semiconductors 29
4.3.2.3 USB 3.0 PLLs
USB 3.0 has two PLLs. One is embedded in Super-Speed PHY. The other one is embedded in the USB 2.0
OTG PHY that is part of the USB 3.0 interface.
The table below describes the PLL embedded in the Super-Speed PHY.
The table below describes the PLL embedded in the USBOTG PHY.
4.3.2.4 USB 2.0 OTG PLLs
This PLL is embedded in the USB 2.0 OTG PHY (the one which is not part of the USB 3.0 feature).
4.3.2.5 PCIe PLLs
The PCIe interface has three PLLs:
• One is used to generate the single, common 100 MHz reference clock to each lane
• One Transmit and one Receive PLL in one lane
Table 17. USB 2.0 PLL embedded in Super Speed PHY
Parameter Value Unit
Reference clock 24 MHz
Clock output frequency 5 GHz
Table 18. USB 2.0 PLL embedded in USBOTG PHY
Parameter Value Unit
Reference clock 24 MHz
Clock output frequency 480 MHz
Table 19. USB 2.0 OTG PLLs
Parameter Value Unit
Reference clock 24 MHz
Clock output frequency 480 MHz