Datasheet

Modules List
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARYNXP Semiconductors 13
3.1 Special Signal Considerations
The package contact assignments can be found in Section 6, “Package information and contact
assignments.” Signal descriptions are defined in the device reference manual.
3.2 Recommended Connections for Unused Interfaces
The recommended connections for unused analog interfaces can be found in the section, “Unused
Input/Output Terminations,” in the hardware development guide for this device.
USBOH The USBOH module has been specified which performs USB 2.0 On-The-Go
(OTG) and USB 2.0 Host functionality compatible with the USB 2.0 with OTG
supplement specification. This controller supports one independent USB core (1
×
USB2.0 OTG) and includes the PHY and I/O interfaces to support this operation.
Key features:
One USB2.0 OTG controller
High Speed (480 Mbps), full speed (12 Mbps) and low speed (1.5 Mbps)
Fully compatible with the USB 2.0 specification
Fully compatible with the USB On-The-Go supplement to the USB 2.0
specification
Hardware support for OTG signaling
Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
implemented in hardware, which can also be controlled by software
uSDHC SD/eMMC and SDXC
Enhanced Multi-Media
Card / Secure Digital
Host Controller
i.MX 8 Family SoC-specific characteristics:
All three MMC/SD/SDIO controller IPs are identical and are based on the uSDHC
IP.
The uSDHC is a host controller used to communicate with external low cost data
storage and communication media. It supports the previous versions of the
MultiMediaCard (MMC) and Secure Digital Card (SD) standards. Specifically, the
uSDHC supports:
SD Host Controller Standard Specification v3.0 with the exception that all the
registers do not match the standards address mapping.
SD Physical Layer Specification v3.0 UHS-I (SDR104/DDR50)
SDIO specification v3.0
eMMC System Specification v5.1
VPU Video Processing Unit See the device reference manual for the complete list of the VPU’s
decoding/encoding capabilities.
WDOG Watchdog The Watchdog Timer supports two comparison points during each counting period.
Each of the comparison points is configurable to evoke an interrupt to the ARM
core, and a second point evokes an external event on the WDOG line.
XTAL OSC24M The 24 MHz clock source is an external crystal that acts as one of two main clock
sources to the chip. The OSC24M is used as the source clock for subsystem PLLs.
OSC24M can be turned off by the System Control Unit (SCU) during sleep mode.
XTAL OSC32K The 32 KHz clock source is an external crystal that is one of two main clock sources
to the chip. The OSC32K is intended to be always on and is distributed by the SCU
to modules in the chip.
Table 2. i.MX 8QuadXPlus/8DualXPlus modules list (continued)
Block
Mnemonic
Block Name Brief Description