Datasheet

Modules List
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARYNXP Semiconductors 11
OCRAM On-Chip Memory
Controller
The On-Chip Memory controller (OCRAM) module is designed as an interface
between the system’s AXI bus and the internal (on-chip) SRAM memory module.
The OCRAM is used for controlling the 256 KB multimedia RAM through a 64-bit
AXI bus.
Parallel CSI Parallel CSI interface The Parallel Port Capture Subsystem interfaces to Parallel CSI sensors and
includes the following features:
Configurable interface logic to support the most commonly used parallel CMOS
sensors
Configurable master clock output to drive external sensor (24 MHz nominal)
Up to 150 MHz input clock from sensor
Input data formats supported:
8-bit/10-bit BT.656
8-bit/24-bit data port for RGB, YCbCr, and YUV data input
8-bit/12-bit/10-bit/16-bit data port for Bayer data input
Note: For some formats a single pixel is sent per clock, for others two or three are
sent per clock.
PCIe PCI Express 3.0 The PCIe IP provides PCI Express Gen 3.0 functionality.
PRG Prefetch/Resolve
Gasket
The PRG is a gasket which translates system memory accesses to local display
RTRAM accesses for display refresh. It works with the DPR to complete the
prefetch and resolving operations needed to drive the display.
PWM Pulse Width Modulation The pulse-width modulator (PWM) has a 16-bit counter and is optimized to
generate sound from stored sample audio images and it can also generate tones.
It uses 16-bit resolution and a 4×16 data FIFO to generate square waveforms.
RAM
16 KB
Secure/non-secure
RAM
Secure/non-secure Internal RAM, interfaced through the CAAM.
RAM
256 KB
Internal RAM Internal RAM, which is accessed through OCRAM memory controllers.
RNG Random Number
Generator
The purpose of the RNG is to generate cryptographically strong random data. It
uses a true random number generator (TRNG) and a pseudo-random number
generator (PRNG) to achieve true randomness and cryptographic strength. The
RNG generates random numbers for secret keys, per message secrets, random
challenges, and other similar quantities used in cryptographic algorithms.
SAI I2S/SSI/AC97 Interface The SAI module provides a synchronous audio interface that supports full duplex
serial interfaces with frame synchronization, such as I2S, AC97, TDM, and
codec/DSP interfaces.
SECO Security Controller Core and associated memory and hardware responsible for key management.
SJC Secure JTAG Controller The SJC provides the JTAG interface, which is compatible with JTAG TAP
standards, to internal logic. This device uses JTAG port for production, testing, and
system debugging. Additionally, the SJC provides BSR (Boundary Scan Register)
standard support, which is compatible with IEEE1149.1 and IEEE1149.6
standards.
The JTAG port must be accessible during platform initial laboratory bring-up, for
manufacturing tests and troubleshooting, as well as for software debugging by
authorized entities. The SJC incorporates three security modes for protecting
against unauthorized accesses. Modes are selected through eFUSE configuration.
Table 2. i.MX 8QuadXPlus/8DualXPlus modules list (continued)
Block
Mnemonic
Block Name Brief Description