Datasheet

Boot mode configuration
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARY NXP Semiconductors108
NAND GPMI EMMC0_CLK, EMMC0_CMD, EMMC0_DATA0,
EMMC0_DATA1, EMMC0_DATA2,
EMMC0_DATA3, EMMC0_DATA4,
EMMC0_DATA5, EMMC0_DATA6,
EMMC0_DATA7, EMMC0_STROBE,
EMMC0_RESET_B, USDHC1_CD_B,
USDHC1_CMD, USDHC1_DATA0,
USDHC1_DATA1, USDHC1_DATA2,
USDHC1_DATA3, USDHC1_RESET_B,
USDHC1_VSELECT, USDHC1_WP
8 bit boot from CS0 only, but will drive CS1 to
high when booting if specified in fuse.
Single-ended DQS:
First (A0) silicon uses EMMC0_CMD.
Second (B0) silicon uses USDHC1_CD_B.
Single-ended RE:
First (A0) silicon uses USDHC1_DATA1.
Second (B0) silicon uses
USDHC1_VSELECT.
Differential DQS:
_N use USDHC1_WP
_P use USDHC1_CD_B
Differential RE:
_N use USDHC1_RESET_B
_P use USDHC1_VSELECT
Quad SPI QSPI0 QSPI0A_DATA0, QSPI0A_DATA1,
QSPI0A_DATA2, QSPI0A_DATA3, QSPI0A_DQS,
QSPI0A_SCLK, QSPI0A_SS0_B,
QSPI0A_SS1_B, QSPI0B_DATA0,
QSPI0B_DATA1, QSPI0B_DATA2,
QSPI0B_DATA3, QSPI0B_DQS, QSPI0B_SCLK,
QSPI0B_SS0_B, QSPI0B_SS1_B
4, dual-4, or 8 bit
USB USB-OTG1 USB_OTG1_DN, USB_OTG1_DP,
USB_OTG1_ID, USB_OTG1_VBUS
Only USB-OTG1 is supported in first silicon (A0);
second silicon (B0) will support both USB-OTG1
and USB-OTG2 .
Table 109. Interface allocation during boot (continued)
Interface IP Instance Allocated Pads During Boot Comment