Datasheet

Modules List
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARY NXP Semiconductors10
KPP Key Pad Port The Keypad Port (KPP) is a 16-bit peripheral that can be used as a 4 x 4 keypad
matrix interface or as general purpose input/output (I/O).
LPIT-1
LPIT-2
Low-Power Periodic
Interrupt Timer
Each LPIT is a 32-bit “set and forget” timer that starts counting after the LPIT is
enabled by software. It is capable of providing precise interrupts at regular intervals
with minimal processor intervention. It has a 12-bit prescaler for division of input
clock frequency to get the required time setting for the interrupts to occur, and
counter value can be programmed on the fly.
LPSPI 0–3 Configurable SPI Full-duplex enhanced Synchronous Serial Interface. It is configurable to support
Master/Slave modes, four chip selects to support multiple peripherals.
M4F ARM (CPU3) Cortex-M4F core
AHB LMEM (Local Memory Controller) including controllers for TCM and cache
memories
256 KB tightly coupled memory(TCM) (128 KB TCMU, 128 KB TCML)
16 KB Code Bus Cache
16 KB System Bus Cache
ECC for TCM memories and parity for code and system caches
Integrated Nested Vector Interrupt Controller (NVIC)
Wakeup Interrupt Controller (WIC)
FPU (Floating Point Unit)
Core MPU (Memory Protection Unit)
Support for exclusive access on the system bus
MMCAU (Crypto Acceleration Unit)
MCM (Miscellaneous Control Module)
MIPI CSI-2 MIPI CSI-2 Interface The MIPI CSI-2 IP provides MIPI CSI-2 standard camera interface ports. The MIPI
CSI-2 interface supports up to 1.5 Gbps for up to 4 data lanes
MIPI-DSI/LVDS MIPI DSI/LVDS Combo
interface
The MIPI DSI IP provides DSI standard display serial interface with 4 data lines.
The DSI interface supports 80 Mbps to 1.05 Gbps speed per data lane.
The LVDS is a high-performance 2-channel serializer that interfaces with LVDS
displays.
Note: This is a combination PHY interface. It includes the digital logic and physical
interface pins for both MIPI DSI (4 data lanes) and LVDS (4 differential pairs plus
one for clock). The interface can be pinned out either as MIPI DSI or as LVDS.
However, it does not allow for simultaneous use on one interface
MOST
®
Media Oriented
Systems Transport
Media local bus interface module that provides a link to a MOST
®
data network,
using the standardized MediaLB protocol. Supports 3-wire interface (MLB25,
MLB50).
MQS Medium Quality Sound Medium Quality Sound (MQS) is used to generate 2-channel medium quality
PWM-like audio via two standard digital GPIO pins.
OCOTP_CTRL OTP Controller The On-Chip OTP controller (OCOTP_CTRL) provides an interface for reading,
programming, and/or overriding identification and control information stored in
on-chip fuse elements. The module supports electrically-programmable poly fuses
(eFUSEs). The OCOTP_CTRL also provides a set of volatile software-accessible
signals that can be used for software control of hardware elements, not requiring
non-volatility. The OCOTP_CTRL provides the primary user-visible mechanism for
interfacing with on-chip fuse elements. Among the uses for the fuses are unique
chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode,
boot characteristics, and various control signals requiring permanent nonvolatility.
Table 2. i.MX 8QuadXPlus/8DualXPlus modules list (continued)
Block
Mnemonic
Block Name Brief Description