Datasheet

Electrical characteristics
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARY NXP Semiconductors90
t2 QSPI
x [A/B]_SS y _B pulse width 1 — SCLK
t3 QSPI
x [A/B]_SS y _B Lead Time
1
(TCSS+0.5)/2 — SCLK
t4 QSPI
x [A/B]_SS y _B Lag Time
1
TCSH/2 — SCLK
t5 QSPI x [A/B]_DATA y output valid time 6.5 1 ns
t6 QSPI x [A/B]_DATA y output hold time 6 — ns
t7 QSPI x [A/B]_DATA y Setup Time 6.5 — ns
t8 QSPI x [A/B]_DATA y Hold Time 0 — ns
1
Timing is controlled from FLSH x CR1 register ( x =A1, A2, B1, or B2).
Table 86. FlexSPI timings with FlexSPI n _MCR0[RXCLKSRC] = 0x1 (DDR mode)
ID Parameter Min Max Unit
— QSPI
x [A/B]_SCLK Cycle frequency — 83 MHz
t1 QSPI x [A/B]_SCLK High or Low Time 5.4 — ns
t2 QSPI x [A/B]_SSy_B pulse width 1 — SCLK
t3 QSPI x [A/B]_SSy_B Lead Time
1
1
Timing is controlled from FLSH x CR1 register ( x =A1, A2, B1, or B2).
(TCSS+0.5)/2 — SCLK
t4 QSPI
x [A/B]_SSy_B Lag Time
1
TCSH/2 — SCLK
t5 QSPI x [A/B]_DATA y output valid time 2 — ns
t6 QSPI x [A/B]_DATA y output hold time 2 — ns
t7 QSPI x [A/B]_DATA y Setup Time 1 — ns
t8 QSPI x [A/B]_DATA y Hold Time 1 — ns
Table 87. FlexSPI timings with FlexSPI n _MCR0[RXCLKSRC] = 0x3 (DDR mode)
ID Parameter Min Max Unit
— QSPI
x [A/B]_SCLK Cycle frequency — 200 MHz
t1 QSPI x [A/B]_SCLK High or Low Time 2.25 — ns
t2 QSPI x [A/B]_SS y _B pulse width 1 — SCLK
t3 QSPI x [A/B]_SS y _B Lead Time
1
(TCSS+0.5)/2 — SCLK
t4 QSPI x [A/B]_SS y _B Lag Time
1
TCSH/2 — SCLK
t5 QSPI x [A/B]_DATA y output valid time 0.65 1 ns
t6 QSPI x [A/B]_DATA y output hold time 0.65 — ns
Table 85. FlexSPI timings with FlexSPI n _MCR0[RXCLKSRC] = 0x0 (DDR mode) (continued)
ID Parameter Min Max Unit