Datasheet

Modules List
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARYNXP Semiconductors 7
3 Modules List
The i.MX 8QuadXPlus/8DualXPlus processors contain a variety of digital and analog modules. This table
describes the processor modules in alphabetical order.
Table 2. i.MX 8QuadXPlus/8DualXPlus modules list
Block
Mnemonic
Block Name Brief Description
ADC Analog-to-Digital
Converter
The analog-to-digital converter (ADC) is a successive approximation ADC
designed for operation within an SoC.
APBH-DMA NAND Flash and BCH
ECC DMA Controller
The AHB-to-APBH bridge provides the chip with a peripheral attachment bus
running on the AHB's HCLK, which includes the AHB-to-APB PIO bridge for a
memory-mapped I/O to the APB devices, as well as a central DMA facility for
devices on this bus and a vectored interrupt controller for the ARM core.
A35 ARM (CPU1) 2–4x Cortex-A35 CPUs with a 32KB L1 instruction cache and a 32 KB data cache.
The CPUs share a 512 KB L2 cache.
ASRC Asynchronous Sample
Rate Converter
The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of
a signal associated to an input clock into a signal associated to a different output
clock. The ASRC supports concurrent sample rate conversion of up to 10 channels
of about -120dB THD+N. The sample rate conversion of each channel is
associated to a pair of incoming and outgoing sampling rates. The ASRC supports
up to three sampling rate pairs.
BCH-62 Binary-BCH ECC
Processor
The BCH62 module provides up to 62-bit ECC for NAND Flash controller (GPMI2)
CAAM Cryptographic
Accelerator and
Assurance Module
CAAM is a cryptographic accelerator and assurance module. CAAM implements
several encryption and hashing functions, a run-time integrity checker, and a
Pseudo Random Number Generator (PRNG).
CAAM also implements a Secure Memory mechanism. In this device the security
memory provided is 64 KB.
CSU Central Security Unit The Central Security Unit (CSU) is responsible for setting comprehensive security
policy within the i.MX 8 Family platform. The Security Control Registers (SCR) of
the CSU are set during boot time by the HAB and are locked to prevent further
writing.
CTI Cross Trigger Interface CTI sends signals across the chip indicating that debug events have occurred. It is
used by features of the Coresight infrastructure.
CTM Cross Trigger Matrix Cross Trigger Matrix IP is used to route triggering events between CTIs.
DAP Debug Access Port The DAP provides real-time access for the debugger without halting the core to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan chains.
DC Display Controller Dual display controller
DDR Controller DRAM Controller • Memory types: LPDDR4 (no ECC) and DDR3L (ECC option)
• One channel of 32-bit memory:
• LPDDR4 up to 1.2 GHz
• DDR3L up to 933MHz