Datasheet

Electrical characteristics
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARYNXP Semiconductors 43
This table shows LPDDR4 I/O on-die termination impedance.
NOTE
• Output driver impedance is controlled across PVTs using ZQ calibration
procedure.
• Calibration is done against 240 Ω external reference resistor.
• Output driver impedance deviation (calibration accuracy) is ±5%
(max/min impedance) across PVTs.
4.8 System Modules Timing
This section contains the timing and electrical parameters for the modules in each processor.
4.8.1 Reset Timing Parameters
The following figure shows the reset timing and Table 41 lists the timing parameters.
Figure 7. Reset timing diagram
Table 40. LPDDR4 I/O on-die termination impedance
Parameter
Typical
Impedance
ZQnPR0. ZPROG_ASYM_PU_DRV
Recommended combinations
for DQ/CA pins
120.0 Ω 3
80.0 Ω 5
60.0 Ω 7
48.0 Ω 9
40.0 Ω 11
Table 41. Reset timing parameters
ID Parameter Min Max Unit
CC1 Duration of SRC_POR_B to be qualified as valid 1 — XTALOSC_RTC_ XTALI cycle
POR_B
CC1
(Input)