Datasheet

Electrical characteristics
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARY NXP Semiconductors30
The table below shows the characteristics for the reference clock PLL.
The table below shows characteristics of the TX and RX PLLs used in each lane.
4.3.2.6 MIPI-DSI/LVDS combo PLL
The table below shows characteristics of the PLL embedded in the MIPI-DSI/LVDS combo PHY.
4.4 On-chip oscillators
4.4.1 OSC24M
This block integrates trimmable internal loading capacitors and driving circuitry. When combined with a
suitable 24 MHz external quartz element, it can generate a low-jitter clock. The oscillator is powered from
VDD_ANA1_1P8. The internal loading capacitors are trimmable to provide fine adjustment of the
24 MHz oscillation frequency. It is expected that customers burn appropriate trim values for the selected
crystal and board parasitics.
Table 20. PCIe reference clock PLLs
Parameter Value Unit Comments
Reference clock 24 MHz —
Clock output frequency 100 MHz Used to generate internal 100 MHz reference clock to PCIe lanes
Table 21. PCIe Transmit and Receive PLLs
Parameter Value Unit Comments
Reference clock 100 MHz From differential input clock pads or from internal PLL
Clock output range 6 ~ 10 GHz PCIe gen3: 8GHz to get 8GHz baud clock
PCIe gen2: 10GHz to get 5GHz baud clock
PCIe gen3: 10GHz to get 2.5GHz baud clock
Table 22. MIPI-DSI/LVDS combo PHY PLL
Parameter Value Unit Comments
Reference clock 24 MHz —
Clock output range 0.75 ~ 1.05 GHz Dependent on targeted display configuration