Datasheet

ManualsBrandsNXP ManualsDevelopment Boards & Kitsi.MX 8QuadMax Multisensory Enablement Kit

Ordering Information

See Section 1.1

Parts in preproduction, limited

availability. For more information,

contact an NXP representative at

nxp.com.

NXP Semiconductors

Data Sheet: Advance Information

IMX8QXPAEC

Rev. 0, 11/2018

Package Information

21 x 21 mm package case outline

17 x 17 mm package case outline

PRELIMINARY

This document contains information on a pre-production product. Specifications and

pre-production information herein are subject to change without notice.

1 Introduction

This data sheet contains specifications for the

i.MX 8QuadXPlus and 8DualXPlus processors, which,

along with the i.MX 8DualX processor, comprise the

i.MX 8X Family (for i.MX 8DualX specifications, see

i.MX 8DualX Automotive and Infotainment Processors

[IMX8DXAEC]). The i.MX 8X processors consist of

three to five ARM

cores (two to four ARM

Cortex

-A35 and one Cortex-M4F). All devices include

separate GPU and VPU subsystems as well as a

failover-ready display controller. Advanced multicore

audio processing is supported by the ARM cores and a

high performance Tensilica

HiFi 4 DSP for pre- and

post-audio processing as well as voice recognition. The

i.MX 8X Family supports up to three displays with

multiple display output options, including parallel,

MIPI-DSI, and LVDS. Memory interfaces for this device

include:

• LPDDR4 (no error correcting code [ECC])

• DDR3L (optional ECC)

i.MX 8QuadXPlus and

8DualXPlus Automotive

and Infotainment

Applications Processors

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 13

3.2 Recommended Connections for Unused Interfaces13

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . . 14

4.2 Power supplies requirements and restrictions. . . . 25

4.3 PLL electrical characteristics. . . . . . . . . . . . . . . . . 27

4.4 On-chip oscillators. . . . . . . . . . . . . . . . . . . . . . . . . 30

4.5 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 33

4.6 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 38

4.7 Output Buffer Impedance Parameters. . . . . . . . . . 39

4.8 System Modules Timing . . . . . . . . . . . . . . . . . . . . 43

4.9 General-Purpose Media Interface (GPMI) Timing. 47

4.10 External Peripheral Interface Parameters . . . . . . . 56

4.11 Analog-to-digital converter (ADC) . . . . . . . . . . . . 104

5 Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 107

5.1 Boot mode configuration pins . . . . . . . . . . . . . . . 107

5.2 Boot devices interfaces allocation . . . . . . . . . . . . 107

6 Package information and contact assignments. . . . . . . 109

6.1 FCPBGA, 21 x 21 mm, 0.8 mm pitch . . . . . . . . . 109

6.2 FCPBGA, 17 x 17 mm, 0.8 mm pitch . . . . . . . . . 126

7 Release notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Summary of content (144 pages)

PAGE 1
NXP Semiconductors Data Sheet: Advance Information IMX8QXPAEC Rev. 0, 11/2018 Parts in preproduction, limited availability. For more information, contact an NXP representative at nxp.com. i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors Package Information 21 x 21 mm package case outline 17 x 17 mm package case outline Ordering Information See Section 1.1 1 Introduction This data sheet contains specifications for the i.
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Introduction • • 2× Quad SPI or 1× Octal SPI (FlexSPI) eMMC 5.1, RAW NAND, and SD 3.0 A wide range of peripheral I/Os such as CAN, parallel or MIPI CSI camera input, Gigabit Ethernet, USB 2.0 OTG, USB 3.0 (8QuadXPlus/8DualXPlus only), ADC, and PCIe 3.0 provide impressive flexibility. The i.MX 8QuadXPlus/8DualXPlus processors offer numerous advanced features as shown in this table. Table 1. i.
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Introduction Table 1. i.MX 8QuadXPlus/8DualXPlus advanced features (continued) Function Memory Feature 32-bit LPDDR4 @1200 MHz 40-bit DDR3L @933 MHz (ECC option) 1× Quad SPI which can be used to connect to an FPGA 2× Quad SPI or 1× Octal SPI (FlexSPI) for fast boot from SPI NOR flash 2× SD 3.0 card interfaces (note: if eMMC is used, then 1× SD 3.0 available in IOMUX) 1× eMMC5.1/SD3.0 (note: use of eMMC will restrict SD card availability to 1× SD 3.
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Introduction Table 1. i.MX 8QuadXPlus/8DualXPlus advanced features (continued) Function I/O Feature 1× PCIe 3.0 (1-lane) with L1 substate support 1× USBOTG 3.0 with PHY—USB 3.0 can be used as USB 2.0 1× USBOTG 2.
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Architectural Overview 1.1 Ordering Information These parts are still in preproduction. For more information, contact an NXP representative at nxp.com. 2 Architectural Overview The following subsections provide an architectural overview of the i.MX 8QuadXPlus/8DualXPlus processor system. i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev.
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Architectural Overview 2.1 Block Diagram The following figure shows the functional modules in the processor system.
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Modules List 3 Modules List The i.MX 8QuadXPlus/8DualXPlus processors contain a variety of digital and analog modules. This table describes the processor modules in alphabetical order. Table 2. i.MX 8QuadXPlus/8DualXPlus modules list Block Mnemonic Block Name Brief Description ADC Analog-to-Digital Converter The analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an SoC.
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Modules List Table 2. i.MX 8QuadXPlus/8DualXPlus modules list (continued) Block Mnemonic Block Name Brief Description DPR Display/Prefetch/ Resolve The DPR prefetches data from memory and converts the data to raster format for display output. Raster source buffers can also be prefetched unconverted. The resolve process supports graphics and video formatted tile frame buffers and converts them to raster format.
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Modules List Table 2. i.MX 8QuadXPlus/8DualXPlus modules list (continued) Block Mnemonic Block Name Brief Description FlexSpi (Quad SPI/Octal SPI) Flexible Serial Peripheral Interface • Flexible sequence engine to support various flash vendor devices, including HyperBus™ devices: • Support for FPGA interface • Single, dual, quad, and octal mode of operation. • DDR/DTR mode wherein the data is generated on every edge of the serial flash clock.
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Modules List Table 2. i.MX 8QuadXPlus/8DualXPlus modules list (continued) Block Mnemonic Block Name Brief Description KPP Key Pad Port The Keypad Port (KPP) is a 16-bit peripheral that can be used as a 4 x 4 keypad matrix interface or as general purpose input/output (I/O). LPIT-1 LPIT-2 Low-Power Periodic Interrupt Timer Each LPIT is a 32-bit “set and forget” timer that starts counting after the LPIT is enabled by software.
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Modules List Table 2. i.MX 8QuadXPlus/8DualXPlus modules list (continued) Block Mnemonic Block Name Brief Description OCRAM On-Chip Memory Controller The On-Chip Memory controller (OCRAM) module is designed as an interface between the system’s AXI bus and the internal (on-chip) SRAM memory module. The OCRAM is used for controlling the 256 KB multimedia RAM through a 64-bit AXI bus.
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Modules List Table 2. i.MX 8QuadXPlus/8DualXPlus modules list (continued) Block Mnemonic Block Name Brief Description SNVS Secure Non-Volatile Storage Secure Non-Volatile Storage, including Secure Real Time Clock, Security State Machine, Master Key Control, and Violation/Tamper Detection and reporting. SPDIF Sony Philips Digital Interconnect Format The Sony/Philips Digital Interface (SPDIF) audio block is a stereo transceiver that allows the processor to receive and transmit digital audio.
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Modules List Table 2. i.MX 8QuadXPlus/8DualXPlus modules list (continued) Block Mnemonic Block Name USBOH Brief Description The USBOH module has been specified which performs USB 2.0 On-The-Go (OTG) and USB 2.0 Host functionality compatible with the USB 2.0 with OTG supplement specification. This controller supports one independent USB core (1× USB2.0 OTG) and includes the PHY and I/O interfaces to support this operation. Key features: • One USB2.
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Electrical characteristics 4 Electrical characteristics This section provides the device and module-level electrical characteristics for these processors. 4.1 Chip-level conditions This section provides the device-level electrical characteristics for the SoC. See the following table for a quick reference to the individual tables and sections. Table 3. Chip-level conditions For these characteristics, … 4.1.
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Electrical characteristics Table 4. Absolute maximum ratings (continued) Parameter Description 1.0V IO supplies Symbol VDD_MIPI_1P0 Min Max Units -0.3 1.2 V -0.5 2.1 V -0.3 3.8 V -0.3 3.8 V VDD_USB_OTG_1P0 IO Supply for GPIO Type 1.
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Electrical characteristics Table 4. Absolute maximum ratings (continued) Parameter Description Symbol Min Max Units -0.3 3.63 V -0.1 2.1 V Vin/Vout input/output voltage range (GPIO Vin/Vout Type Pins) -0.3 OVDD+0.31 V Vin/Vout input/output voltage range (DDR pins) Vin/Vout -0.3 OVDD+0.41,2 V ESD immunity (HBM). All pins except PCIe differential pairs, HDMI-RX, HDMI-TX, and USB3 (including OTG2) interfaces. Vesd_HBMX — 2000 V ESD immunity (CDM).
PAGE 17
Electrical characteristics Table 5. FCPBGA package thermal resistance data1 (continued) Thermal Parameter Junction to Ambient1 Test Conditions 1 2 3 4 5 6 21x21 mm 17x17 mm package package Unit Single-layer board (1s); air flow 200 ft/min4 RθJMA 17.6 20.0 °C/W Four-layer board (2s2p); air flow 200 ft/min4 RθJMA 10.5 11.0 °C/W — RθJB 2.9 2.1 °C/W — RθJCtop 0.7 0.
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Electrical characteristics Table 6. Operating ranges1 (continued) Symbol VDD_DDR_VDDQ Description Power supplies of memory IOs Mode Min Typ Max Unit Comments DDR3L 1.30 1.35 1.45 V Max frequency: 933 MHz to support DDR3L-1866 LPDDR4 1.06 1.10 1.17 V Max frequency: 1.2GHz to support LPDDR4-2400 PLL supply can be merged with other 1.8V supplies with proper on board decoupling. VDD_DDR_PLL_1P8 Power supplies of memory PLLs N/A 1.65 1.80 1.95 V VDD_MIPI_1P0 Power supplies of PHYs (1.
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Electrical characteristics Table 6. Operating ranges1 (continued) Symbol VDD_CAN_UART_1P8_3P3 VDD_CSI_1P8_3P3 VDD_EMMC0_1P8_3P3 VDD_EMMC0_VSELECT_1P8_3P3 VDD_ENET_MDIO_1P8_3P3 VDD_MIPI_DSI_DIG_1P8_3P3 VDD_PCIE_DIG_1P8_3P3 VDD_QSPI0A_1P8_3P3 VDD_QSPI0B_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_SPI_SAI_1P8_3P3 VDD_TMPR_CSI_1P8_3P3 VDD_USDHC1_1P8_3P3 VDD_USDHC1_VSELECT_1P8_3P3 Description Power supplies of GPIO supporting both 1.8V or 3.3V Mode Min Typ Max Unit 1.8V 1.65 1.80 1.
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Electrical characteristics Table 6. Operating ranges1 (continued) Symbol Description Mode Min Typ Max Unit Comments Power supplies that shall be connected to output of an embedded LDO VDD_TMPR_CSI_1P8_3P3 — N/A — 1.80 — V Shall be internally connected to VDD_SNVS_LDO_1P8_ CAP when used as a tamper pin. In CSI mode use an external 1.8 V supply. In this case, follow the 1.8 V I/O specification above. VDD_USB_OTG_1P0 — N/A — 1.
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Electrical characteristics 2 The required frequency stability of this clock source is application dependent. For recommendations, see the Hardware Development Guide. 3 Recommended nominal frequency 32.768 kHz. 4 Fundamental frequency crystal with internal oscillator amplifier. 5 If using an external clock instead of the internal clock source, an HCSL-compatible clock is required.
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Electrical characteristics Table 8.
PAGE 23
Electrical characteristics Table 9. Standby use cases (continued) Mode CM4 Standby Test conditions CM4 TCM in retention Other voltage domains not considered i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev.
PAGE 24
Electrical characteristics 4.1.7 USB 2.0 PHY typical current consumption in Power-Down mode In power down mode, everything is powered down, including the VBUS valid detectors, typical condition. The following table shows the USB interface typical current consumption in Power-Down mode. Table 10. USB 2.0 PHY typical current consumption in Power-Down Mode Current 4.1.8 VDD_USB_3P3 (3.3 V) VDD_USB_1P8 (1.8 V) VDD_USB_OTG_1P0 (1.0 V) 1 μA 0.06 μA 0.5 μA USB 3.
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Electrical characteristics 4.2 Power supplies requirements and restrictions The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to ensure the reliable operation of the device. Any deviation from these sequences may result in the following situations: • Excessive current during power-up phase • Prevention of the device from booting • Irreversible damage to the processor 4.2.
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Electrical characteristics 26 Table 13. Power supplies usage PRELIMINARY NXP Semiconductors i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018 Supply Groups Group 0 Group 1 Voltage 2.4 - 4.2v 1.8v internal LDO VDD_SNVS_4P2 VDD_TMPR_CSI_1P8_3P31 1.0v 1.8v VDD_MAIN VDD_ANAx_1P8 VDD_MIPI_1P0 1.2 - 1.35v 1.8v 1.8v or 3.3v 1.8v or 3.3v switchable 3.
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Electrical characteristics 4.3 PLL electrical characteristics 4.3.1 PLLs of subsystems i.MX 8QuadXPlus/8DualXPlus embeds a large number of PLLs to address clocking requirements of the various subsystems. These PLLs are controlled through the SCU and not directly by Cortex-A or Cortex-M4F processors. A software API shall be used by those processors to access the PLL settings. Additional PLLs are specific to high-performance interfaces. These are described in the following sections.
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Electrical characteristics Table 14. PLLs controlled by SCU (continued) Locking range1 Subsystem PLL usage Source clock Min freq. Max freq. Lock freq. Unit MIPI-DSI Subsystem 24 650 1300 864 MHz MIPI-CSI Subsystem 24 650 1300 720 MHz SCU (System Controller Unit) Subsystem 24 650 1300 1056 MHz 1 Operating frequencies are limited to only those supported by the SCFW. 1200 MHz is used to generate the max frequency points, and 1000 MHz for the typical frequency point.
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Electrical characteristics 4.3.2.3 USB 3.0 PLLs USB 3.0 has two PLLs. One is embedded in Super-Speed PHY. The other one is embedded in the USB 2.0 OTG PHY that is part of the USB 3.0 interface. The table below describes the PLL embedded in the Super-Speed PHY. Table 17. USB 2.0 PLL embedded in Super Speed PHY Parameter Value Unit Reference clock 24 MHz Clock output frequency 5 GHz The table below describes the PLL embedded in the USBOTG PHY. Table 18. USB 2.
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Electrical characteristics The table below shows the characteristics for the reference clock PLL. Table 20. PCIe reference clock PLLs Parameter Value Unit Comments Reference clock 24 MHz — Clock output frequency 100 MHz Used to generate internal 100 MHz reference clock to PCIe lanes The table below shows characteristics of the TX and RX PLLs used in each lane. Table 21. PCIe Transmit and Receive PLLs Parameter Reference clock Clock output range 4.3.2.
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Electrical characteristics Figure 2. Normal Crystal Oscillation mode Table 23. Crystal specifications Parameter description Min Typ Max Unit Frequency1 — 24 — MHz Cload2 — 18 — pF 200 — — μW — 50 — Ω Maximum drive level ESR 1 The required frequency accuracy is set by the serial interfaces utilized for a specific application and is detailed in the respective standard documents. 2 Cload is the specification of the quartz element, not for the capacitors coupled to the quartz element.
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Electrical characteristics CAUTION The internal oscillator provides an estimated frequency accuracy of ±5%, subject to silicon validation, and is affected by process, voltage and temperature variations. NXP strongly recommends using an external crystal to implement an oscillator. If the internal oscillator is used instead, careful consideration must be given to the timing implications on all of the SoC modules dependent on this clock. The OSC32K runs from VDD_SNVS_1p8_CAP, which is regulated from VDD_SNVS.
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Electrical characteristics 4 The rise/fall time of the applied clock are not strictly confined. 4.5 I/O DC Parameters This section includes the DC parameters of the following I/O types: • XTALI and RTC_XTALI (clock inputs) DC parameters • General Purpose I/O (GPIO) DC parameters NOTE The term ‘OVDD’ in this section refers to the associated supply rail of an input or output. ovdd pmos (Rpu) 1 or 0 pdat Voh min Vol max pad Predriver nmos (Rpd) ovss Figure 3.
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Electrical characteristics Table 26. Dual-voltage GPIO 3.3V DC parameters1 (IO PSW is set to 1.8 V Range) (continued) Parameter Symbol Low-level output voltage3 VOL Test Conditions2 Min Max Units — 0.125 × OVDD V Iol= -0.1mA DSE=1 Iol= -2mA DSE=0 High-Level input voltage3,4 VIH — 0.625 × OVDD OVDD V Low-Level input voltage VIL — 0 0.
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Electrical characteristics Table 27. Dual-voltage GPIO 3.3 V DC parameters1 (IO PSW is set to 3.3 V range) (continued) Parameter Pull-down resistance Input current (no PU/PD) Symbol Test Conditions2 Min Max Units Rdown Vin=OVDD( Pulldown Resistor) PUN = "H", PDN = "L" 10 100 kΩ IIN VI = 0, VI = OVDD PUN = "H", PDN = "H" -2 2 μA 1 PSW (Supply Mode Selection) set to "H" High Voltage. See Table 34.
PAGE 36
Electrical characteristics Table 28. Single-voltage 1.8 V GPIO DC parameters (continued) Symbol Test Conditions1 Min Max Units Input current (no PU/PD) IIN VI = 0, VI = OVDD PUN = "H", PDN = "H" -5 5 μA Keeper Circuit Resistance R_Keeper VI =.3xOVDD, VI = .7x OVDD PUN = "L", PDN = "L" 15 90 kΩ Parameter 1 See .Table 35 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.
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Electrical characteristics 3 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 ns. 4.5.3 DDR I/O DC parameters The DDR I/O pads support LPDDR4 and DDR3L operational modes. 4.5.3.1 LPDDR4 mode I/O DC parameters These parameters are guaranteed per the operating ranges in Table 6 unless otherwise noted. Table 30.
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Electrical characteristics Table 31. SSTL DDR3L DC parameters (continued) Parameter Symbol Input current (no ODT) IIN Test Conditions VI = VSSQ, VI = VDDQ Min Max Units -2 2 μA DC High-Level input voltage VIH_DC VREF + 0.09 VDDQ V DC Low-Level input voltage VIL_DC VSSQ VREF – 0.09 V 1 Maximum peak amplitude allowed for overshoot and undershoot area = 0.35 V. Maximum overshoot area above VDD/VDDQ 0.8 V-ns; maximum undershoot area below VSS/VSSQ 0.8 V-ns. 4.
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Electrical characteristics Table 32. General Purpose I/O AC Parameters1 (continued) Symbol fmax Parameter Maximum frequency Test Condition Min Typ Max Unit Load = 30 pF — — 52 MHz tr Rise time Measured between VOL and VOH — — 3 ns tf Fall time Measured between VOH and VOL — — 3 ns 1 All output I/O specifications are guaranteed for Accurate mode of the compensation cell operation. This is applicable for both DC and AC specifications. 2 All timing specifications in 1.
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Electrical characteristics NOTE GPIO and DDR I/O output driver impedance is measured with “long” transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see Figure 6).
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Electrical characteristics 4.7.1 4.7.1.1 GPIO output buffer impedance Dual-voltage GPIO output buffer impedance Table 34. Dual-voltage GPIO output drive selection truth table Drive strength1 Description 1 Output is configured in Low Drive mode recommended for SD standard (1.8 V mode). 0 Output is configured in High Drive mode recommended for SD standard (3.3 V mode) and MMC standard (1.8 V/3.3 V modes). 1 As programmed in the associated IOMUX (PDRV field) register. 4.7.1.2 1.
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Electrical characteristics 4.7.2 DDR I/O output buffer impedance The following tables show DDR3L and LPDDR4 I/O output buffer impedance of the device.The ZQ Calibration cell uses a single register (ZQnPR0) to determine the target output buffer impedances of the pull-up driver and the pull-down driver, as well as the target on-die termination impedance. The resulting calibration setting is then applied to all DDR pads within the PHY complex.
PAGE 43
Electrical characteristics This table shows LPDDR4 I/O on-die termination impedance. Table 40. LPDDR4 I/O on-die termination impedance Parameter Typical Impedance ZQnPR0. ZPROG_ASYM_PU_DRV 120.0 Ω 3 80.0 Ω 5 60.0 Ω 7 48.0 Ω 9 40.0 Ω 11 Recommended combinations for DQ/CA pins • • • 4.8 NOTE Output driver impedance is controlled across PVTs using ZQ calibration procedure. Calibration is done against 240 Ω external reference resistor.
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Electrical characteristics 4.8.2 WDOG reset timing parameters The following figure shows the WDOG reset timing and Table 42 lists the timing parameters. Figure 8. SCU_WDOG_OUT timing diagram Table 42. WDOG1_B timing parameters ID Parameter CC3 Duration of SCU_WDOG_OUT assertion Min Max Unit 1 — XTALOSC_RTC_ XTALI cycle NOTE XTALOSC_RTC_XTALI is approximately 32 kHz. XTALOSC_RTC_XTALI cycle is one period or approximately 30 μs. 4.8.3 DDR SDRAM–specific parameters (LPDDR4 and DDR3L) The i.
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Electrical characteristics www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-proc essors/i.mx-8-processors:IMX8-SERIES. Processors that demonstrate full DDR performance on NXP validated designs, but do not function on customer designs, are not considered marginal parts. A report detailing how the returned part behaved on an NXP validated system will be provided to the customer as closure to a customer’s reported DDR issue.
PAGE 46
Electrical characteristics Table 44.
PAGE 47
Electrical characteristics 4.8.3.2 ECC for DDR3L i.MX 8QuadXPlus/8DualXPlus supports up to 8-bit ECC when using DDR3L only. This is accomplished through the use of a fifth byte lane (DQS4[P:N],DM4, DQ[32:39]). When using the fifth byte lane, it is not a requirement that all DDR3L devices be identical, but it is required that all devices be able to operate with the same timing parameters. This can be easily accomplished by using memory containing the same die(s), but contained in different packages.
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Electrical characteristics 4.9.1 GPMI Asynchronous mode AC timing (ONFI 1.0 compatible) Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The Maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 9 through Figure 12 depict the relative timing between GPMI signals at the module level for different operations under Asynchronous mode. Table 45 describes the timing parameters (NF1–NF17) that are shown in the figures. .!.$?#,% .!.
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Electrical characteristics .!.$?#,% .!.$?#% ?" E&ϭϰ .!.$?2%?" .!.$?2%!$9?" E&ϭϯ E&ϭϱ E&ϭϮ E&ϭϲ .!.$?$!4!XX E&ϭϳ ĂƚĂ ĨƌŽŵ E& Figure 12. Read Data Latch Cycle Timing Diagram (Non-EDO Mode) .!.$?#,% .!.$?#% ?" E&ϭϰ E&ϭϯ .!.$?2%?" .!.$?2%!$9?" E&ϭϱ E&ϭϮ E&ϭϳ E&ϭϲ E E ͺ d ǆǆ ĂƚĂ ĨƌŽŵ E& Figure 13. Read Data Latch Cycle Timing Diagram (EDO Mode) Table 45.
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Electrical characteristics Table 45. Asynchronous Mode Timing Parameters1 (continued) ID Parameter Timing T = GPMI Clock Cycle Symbol Unit Min Max NF16 Data setup on read tDSR — (DS × T -0.67)/18.38 [see 5,6] ns NF17 Data hold on read tDHR 0.82/11.83 [see 5,6] — ns 1 2 3 4 5 6 The GPMI asynchronous mode output timing can be controlled by the module’s internal registers HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
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Electrical characteristics 4.9.2 GPMI Source Synchronous mode AC timing (ONFI 2.x compatible) The following figure shows the write and read timing of Source Synchronous mode. 1) 1) .!.$?#%?" 1) 1$1'B&/( 1) 1) 1) 1$1'B$/( 1) 1) 1$1'B:( 5(B% 1) 1$1'B&/. 1$1'B'46 1$1'B'46 2XWSXW HQDEOH 1) 1) 1) 1) 1$1'B'$7$> @ $'' &0' 1$1'B'$7$> @ 2XWSXW HQDEOH Figure 14. Source Synchronous Mode Command and Address Timing Diagram i.
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Electrical characteristics .!.$?#% ?" 1) 1) 1) .!.$?#,% 1) 1) 1) 1) 1) .!.$?!,% 1) 1) 1$1'B:( 5(B% 1) .!.$?#,+ 1) 1) .!.$?$13 .!.$?$13 2XWSXW HQDEOH 1) 1) .!.$?$1; = 1) 1) .!.$?$1; = 2XWSXW HQDEOH Figure 15. Source Synchronous Mode Data Write Timing Diagram .!.$?#%?" 1) 1) 1) 1) .!.$?#,% 1$1'B$/( .!.$?7% 2% 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) .!.$?#,+ .!.$?$13 .!.$?$13 /UTPUT ENABLE .!.$?$!4!; = .!.
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Electrical characteristics .!.$?$13 E&ϯϬ .!.$?$!4!; = Ϭ E&ϯϬ ϭ E&ϯϭ Ϯ ϯ E&ϯϭ Figure 17. NAND_DQS/NAND_DQ Read Valid Window Table 46. Source Synchronous Mode Timing Parameters1 ID Parameter Symbol Timing T = GPMI Clock Cycle Min NF18 NAND_CEx_B access time tCE NF19 NAND_CEx_B hold time tCH Unit Max CE_DELAY × T - 0.79 [see 2] 0.5 × tCK - 0.63 [see 2] ns ns NF20 Command/address NAND_DATAxx setup time tCAS 0.5 × tCK - 0.
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Electrical characteristics 4.9.3 4.9.3.1 ONFI NV-DDR2 mode (ONFI 3.2 compatible) Command and address timing ONFI 3.2 mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing. See Section 4.9.1, “GPMI Asynchronous mode AC timing (ONFI 1.0 compatible),” for details. 4.9.3.2 Read and write timing ONFI 3.2 mode read and write timing is the same as Toggle mode AC timing. See Section 4.9.4, “Toggle mode AC Timing,” for details. 4.9.4 4.9.4.
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Electrical characteristics DEV?CLK .!.$?#%X?" .& .!.$?#,% .!.$?!,% .!.$?7%?" T #+ .& T #+ .& .!.$?2%?" T #+ T #+ T #+ .!.$?$13 .!.$?$!4!; = Figure 19. Toggle mode data read timing Table 47. Toggle mode timing parameters1 ID Parameter Timing T = GPMI Clock Cycle Symbol Min. Unit Max. (AS + DS) × T - 0.12 [see note2s,3] NF1 NAND_CLE setup time tCLS NF2 NAND_CLE hold time tCLH DH × T - 0.72 [see note2] NF3 NAND_CE0_B setup time tCS (AS + DS) × T - 0.
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Electrical characteristics Table 47. Toggle mode timing parameters1 (continued) ID Parameter Symbol Timing T = GPMI Clock Cycle Unit Min. Max. NF28 Data write setup tDS6 0.25 × tCK - 0.32 — ns NF29 Data write hold tDH6 0.25 × tCK - 0.79 — ns NF30 NAND_DQS/NAND_DQ read setup skew tDQSQ7 — 3.18 NF31 NAND_DQS/NAND_DQ read hold skew tQHS7 — 3.
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Electrical characteristics Below are the LPSPI interfaces and their respective chip selects: Table 48. LPSPI interfaces and chip selects LPSPI interface Chip select 60 MHz in Master mode and 40 MHz in Slave mode SPI0, SPI2, SPI2b, SPI3 40 MHz in Master mode and 20 MHz in Slave mode SPI1, SPI1b, SPI2c+ 4.10.1.1 Comment — LPSPI Master mode Waveform is assuming LPSPI is configured in mode 0, i.e. TCR.CPOL=0b0 and TCR.CPHA=0b0.
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Electrical characteristics Table 49. LPSPI timings—Master mode at 60 MHz (continued) ID Parameter Min Max Unit t5 SPIx_SDO output Delay (CLOAD = 20 pF) — 3 ns t6 SPIx_SDI Setup Time 2 — ns t7 SPIx_SDI Hold Time 2 — ns 1 This timing is controllable through CCR.PCSSCK and TCR.PRESCALE registers. FCLK_PERIOD is the period of the functional clock provided to LPSPI module. Maximum allowed frequency is 240 MHz. 3 This timing is controllable through CCR.SCKPCS and TCR.PRESCALE registers.
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Electrical characteristics Figure 21. LPSPI Slave mode Table 51.
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Electrical characteristics Table 52. LPSPI timings—Slave mode at 20 MHz (continued) ID Parameter Min Max Unit t4 SPIx_CSy Lag Time (CS hold time) 2 — ns t5 SPIx_SDO output Delay (CLOAD = 20 pF) — 18 ns t6 SPIx_SDI Setup Time 2 — ns t7 SPIx_SDI Hold Time 2 — ns 4.10.2 Serial audio interface (SAI) timing parameters The timings and figures in this section are valid for noninverted clock polarity (I2S_TCR2.BCP = 0b0, I2S_RCR2.BCP = 0b0) and non-inverted frame sync polarity (I2S_TCR4.
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Electrical characteristics Table 53. SAI timings—Master Synchronous mode ID Parameters Min Max Unit — 49.152 MHz 45% 55% SAI_TXC period — SAI TXC clock frequency t1 SAI TXC pulse width low / high t2 SAI TXFS output valid — 2 ns t3 SAI TXD output valid — 2 ns t4 SAI RXD input setup 1 — ns t5 SAI RXD input hold 4 — ns 4.10.2.2 SAI Master mode In this mode, transmitter and/or receiver part are set to bring out transmit and/or receive clock.
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Electrical characteristics Table 54. SAI timings—Master mode (continued) ID 1 Parameters Min Max Unit t3 SAI TXD output valid — 2 ns t4 SAI RXD/RXFS/TXFS input setup 6 — ns t5 SAI RXD/RXFS/TXFS input hold 0 — ns Given the high setup time requirement on inputs, receiver and transmitter, when using frame sync in input, are likely to run at a lower frequency. This frequency will be driven by characteristics of the external component connected to the interface. 4.10.2.
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Electrical characteristics 4.10.3 Enhanced serial audio interface (ESAI) The same performance is achieved at both 1.8 V and 3.3 V unless otherwise stated. SCKT (Input / Output) t1 t1 FST (bit) out 2t 2t FST (word) out 2t 2t Data Out Last bit First bit t3 4t t3 t4 FST (bit) in t5 t6 FST (word) in t5 t6 Flags Out t7 Figure 25. ESAI Transmit timing i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev.
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Electrical characteristics Figure 26. ESAI Receive timing The following table shows the interface timing values. The ID field in the table refers to timing signals found in Figure 25 and Figure 26. Table 56. Enhanced Serial Audio Interface (ESAI) Timing ID Parameters Min Max Condition1 Unit — Clock frequency — 24.
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Electrical characteristics Table 56.
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Electrical characteristics 4.10.4.1 SD3.1/eMMC5.1 High-Speed mode AC Timing The following figure depicts the timing of SD3.1/eMMC5.1 High-Speed mode, and Table 57 lists the timing characteristics. SD4 SD2 SD1 SD5 SDx_CLK SD3 SD6 Output from uSDHC to card SDx_DATA[7:0] SD7 SD8 Input from card to uSDHC SDx_DATA[7:0] Figure 27. SD3.1/eMMC5.1 High-Speed mode Timing Table 57. SD3.1/eMMC5.
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Electrical characteristics 3 In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock frequency can be any value between 0–52 MHz. 4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. 4.10.4.2 eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode timing The following figure depicts the timing of eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode, and Table 58 lists the timing characteristics.
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Electrical characteristics HS400 mode is the same as CMD input/output timing for SDR104 mode. Check SD5, SD6 and SD7 parameters in Table 61 SDR50/SDR104 Interface Timing Specification for CMD input/output timing for HS400 mode. Figure 30. HS400 timing Table 59. HS400 interface timing specifications ID Parameter Symbols Min Max Unit Card Input clock SD1 Clock Frequency fPP 0 200 Mhz SD2 Clock Low Time tCL 0.46 × tCLK 0.54 × tCLK ns SD3 Clock High Time tCH 0.46 × tCLK 0.
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Electrical characteristics 4.10.4.4 HS200 Mode Timing The following figure depicts the timing of HS200 mode, and Table 60 lists the HS200 timing characteristics. 6' 6' 6' 6&. 6' 6' ELW RXWSXW IURP X6'+& WR H00& 6' 6' ELW LQSXW IURP H00& WR X6'+& 6' Figure 31. HS200 Mode Timing Table 60. HS200 Interface Timing Specification ID Parameter Symbols Min Max Unit Card Input Clock SD1 Clock Frequency Period tCLK 5.0 — ns SD2 Clock Low Time tCL 0.46 × tCLK 0.
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Electrical characteristics 4.10.4.5 SDR50/SDR104 AC Timing The following figure depicts the timing of SDR50/SDR104, and Table 61 lists the SDR50/SDR104 timing characteristics. 6' 6' 6' 6&. 6' 6' 2XWSXW IURP X6'+& WR FDUG 6' 6' ,QSXW IURP FDUG WR X6'+& 6' Figure 32. SDR50/SDR104 timing Table 61. SDR50/SDR104 Interface Timing Specification ID Parameter Symbols Min Max Unit Card Input Clock SD1 Clock Frequency Period tCLK 4.8 — ns SD2 Clock Low Time tCL 0.46 × tCLK 0.
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Electrical characteristics 4.10.4.6 Bus Operation Condition for 3.3 V and 1.8 V Signaling Signaling level of SD/eMMC 5.1 and eMMC 5.1 modes is 3.3 V. Signaling level of SDR104/SDR50 mode is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2, and NVCC_SD3 supplies are identical to those shown in “,” and Table 26, "Dual-voltage GPIO 3.3V DC parameters (IO PSW is set to 1.8 V Range)," on page 33Table 27, "Dual-voltage GPIO 3.3 V DC parameters (IO PSW is set to 3.3 V range)," on page 34. 4.10.
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Electrical characteristics 4.10.5.1 4.10.5.1.1 RGMII No-Internal-Delay mode This mode corresponds to the RGMIIv1.3 specification. Figure 33. RGMII timing diagram—No-Internal-Delay mode Table 63. RGMII timings—No-Internal-Delay mode ID 1 Parameter Min Typ Max Unit TXC / RXC frequency — — 125 MHz t1 Clock cycle 7.2 8 8.8 ns t2 Data to clock output skew -500 — 500 ps t3 Data to clock input skew1(1) 1 — 2.
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Electrical characteristics Figure 34. RGMII timing diagram—Internal-Delay mode Table 64. RGMII timing—Internal-Delay mode ID Parameter Min Typ TXC / RXC frequency Max Unit 125 MHz t1 Clock cycle 7.2 8 8.8 ns t2 TXD setup time 1.2 — — ns t3 TXD hold time 1.2 — — ns t4 RXD setup time 0 — — ns t5 RXD hold time 2.5 — — ns i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev.
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Electrical characteristics 4.10.5.2 RMII Figure 35. RMII timing diagram The RMII timing parameters table is TBD. 4.10.6 CAN network AC Electrical Specifications The Flexible Controller Area Network (FlexCAN) module is a communication controller implementing the CAN protocol according to the CAN with Flexible Data rate (CAN FD) protocol and the CAN 2.0B protocol specification. The processor has three CAN modules available for systems design.
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Electrical characteristics 4.10.7 I2C Module Timing Parameters This section describes the timing parameters of the I2C module. The following figure depicts the timing of the I2C module, and Table 65 lists the I2C module timing characteristics. I2Cx_SDA IC11 IC10 IC2 IC7 IC4 IC8 IC9 IC3 I2Cx_SCL START IC10b IC11b IC6 STOP START START IC5 IC1 Figure 36. I2C bus timing Table 65.
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Electrical characteristics Table 66. I2C timing High Speed1 Fast Mode Plus Unit ID Parameter Min Max Min Max — 1 — 3.
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Electrical characteristics 4.10.8.2 LVDS display bridge (LDB) module electrical specifications The MIPI DSI/LVDS interface is compatible with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits.” Table 67. LVDS Display Bridge (LDB) Electrical Specifications Parameter Symbol Test Condition Min Max Units 0.25 0.
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Electrical characteristics Table 69. MIPI high-speed transmitter AC specifications Symbol Parameter Min Typ Max Unit ΔVCMTX(HF) Common-level variations above 450 MHz — — 15 mVRMS ΔVCMTX(LF) Common-level variation between 50-450 MHz — — 25 mVPEAK tR and tF1 Rise Time and Fall Time (20% to 80%) 100 — 0.35 UI ps 1 UI is the long-term average unit interval. 4.10.8.4 MIPI-DSI LP-TX specifications Table 70.
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Electrical characteristics 3 With an additional load capacitance CCM between 0 to 60 pF on the termination center tap at RX side of the lane. This parameter value can be lower then TLPX due to differences in rise vs. fall signal slopes and trip levels and mismatches between Dp and Dn LP transmitters. Any LP exclusive-OR pulse observed during HS EoT (transition from HS level to LP-11) is glitch behavior as described in Low-Power Receiver section.
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Electrical characteristics 4.10.8.7 MIPI-DSI DC specifications Table 75. MIPI input characteristics DC specifications Symbol Parameter VPIN ILEAK 1 VGNDSH VPIN(absmax) 2 Min Typ Max Unit Pad signal voltage range –50 — 1350 mV Pin leakage current –10 — 10 μA Ground shift –50 — 50 mV –0.15 — 1.
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Electrical characteristics Figure 37. TX and RX eye diagram template Table 76. PCIe transmitter eye specifications for example standards UI AOPENING BOPENING AOPENING BOPENING ps UI VDIFFp-pmin ps VDIFFp-pmax mV PCI Express Gen 1 Transition Bit 400 0.75 0 300 0 800 12001 PCI ExpressGen 1 De-emphasized Bit 400 0.75 0 300 0 505 757 PCI Express Gen 2 Transition Bit 200 0.75 0 150 0 800 12001 PCI Express Gen 2 De-emphasized Bit 200 0.
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Electrical characteristics Table 78.
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Electrical characteristics 4.10.9.1 PCIE_REXT reference resistor connection The following figure shows the PCIE_REXT reference resistor connection. Figure 38. PCIE_REXT reference resistor connection 4.10.9.2 PCIE_REF_CLK Pin names: • PCIE_[SATA]_REFCLK100M_P • PCIE_[SATA]_REFCLK100M_N TBD 4.10.10 Pulse Width Modulator (PWM) Timing Parameters This section describes the electrical information of the PWM. The PWM can be programmed to select one of three clock signals as its source frequency.
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Electrical characteristics Table 79. PWM Output Timing Parameters (continued) P1 PWM output pulse width high 15 — ns P2 PWM output pulse width low 15 — ns 4.10.11 LCD controller (LCDIF) parameters Figure 40 shows the LCDIF timing, and Table 80 lists the timing parameters. / / / /&'QB&/. IDOOLQJ HGJH FDSWXUH /&'QB&/. ULVLQJ HGJH FDSWXUH /&'QB'$7$> @ /&'Q &RQWURO 6LJQDOV / / / / Figure 40. LCD Timing Table 80.
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Electrical characteristics Table 81.
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Electrical characteristics Table 81. LCD Signal Parameters (continued) LCD_D1 B[1] B[1] B[1] B[1] Y/C[1] LCD_D0 B[0] B[0] B[0] B[0] Y/C[0] LCD_RESET LCD_RESET LCD_RESET LCD_RESET LCD_RESET — LCD_BUSY / LCD_VSYNC LCD_BUSY (or optional LCD_VSYNC) LCD_BUSY (or optional LCD_VSYNC) LCD_BUSY (or optional LCD_VSYNC) LCD_BUSY (or optional LCD_VSYNC) — 4.10.12 FlexSPI (Quad SPI/Octal SPI) timing parameters The FlexSPI interface can work in SDR or DDR modes. It can operate up to 60 MHz at 3.
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Electrical characteristics The following read timing diagram is valid for FlexSPIn_MCR0[RXCLKSRC] = 0x0 or 0x1. Figure 42. FlexSPI read timing diagram (SDR mode) The following read timing diagram is valid for FlexSPIn_MCR0[RXCLKSRC] = 0x3. Figure 43. FlexSPI read with DQS timing diagram (SDR mode) 4.10.12.1.2 SDR mode timing parameter tables Table 82.
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Electrical characteristics Table 83. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x1 (SDR mode) ID 1 Parameter Min Max Unit — QSPIx[A/B]_SCLK Cycle frequency — 166 MHz t1 QSPIx[A/B]_SCLK High or Low Time 2.7 — ns t2 QSPIx[A/B]_SSy_B pulse width 1 — SCLK t3 QSPIx[A/B]_SSy_B Lead Time1 TCSS+0.
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Electrical characteristics 4.10.12.2 DDR mode 4.10.12.2.1 DDR mode timing diagrams Figure 44. FlexSPI write timing diagram (DDR mode) Figure 45. FlexSPI read timing diagram (DDR mode) Figure 46. FlexSPI read with DQS timing diagram (DDR mode) Table 85. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x0 (DDR mode) ID Parameter Min Max Unit — QSPIx[A/B]_SCLK Cycle frequency — 30 MHz t1 QSPIx[A/B]_SCLK High or Low Time 15 — ns i.
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Electrical characteristics Table 85. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x0 (DDR mode) (continued) ID 1 Parameter Min Max Unit t2 QSPIx[A/B]_SSy_B pulse width 1 — SCLK t3 QSPIx[A/B]_SSy_B Lead Time1 (TCSS+0.5)/2 — SCLK TCSH/2 — SCLK 1 t4 QSPIx[A/B]_SSy_B Lag Time t5 QSPIx[A/B]_DATAy output valid time 6.5 1 ns t6 QSPIx[A/B]_DATAy output hold time 6 — ns t7 QSPIx[A/B]_DATAy Setup Time 6.
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Electrical characteristics Table 87. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x3 (DDR mode) (continued) ID 1 Parameter Min Max Unit t9 QSPIx[A/B]_DATAy Setup Time 0.65 — ns t10 QSPIx[A/B]_DATAy Hold Time 0.65 — ns Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). 4.10.13 Secure JTAG controller (SJC) 4.10.13.1 Internal pull-up/pull-down configuration The following table describes the default configuration of internal pull-ups and pull-downs of the JTAG interface.
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Electrical characteristics JTAG_TCK (Input) VIH VIL SJ5 SJ4 Data Inputs Input Data Valid SJ6 Data Outputs Output Data Valid SJ7 Data Outputs SJ6 Data Outputs Output Data Valid Figure 48. Boundary system (JTAG) timing diagram JTAG_TCK (Input) VIH VIL SJ8 JTAG_TDI JTAG_TMS (Input) SJ9 Input Data Valid SJ10 JTAG_TDO (Output) Output Data Valid SJ11 JTAG_TDO (Output) SJ10 JTAG_TDO (Output) Output Data Valid Figure 49. Test Access Port Timing Diagram i.
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Electrical characteristics JTAG_TCK (Input) SJ13 JTAG_TRST_B (Input) SJ12 Figure 50. JTAG_TRST_B Timing Diagram Table 89. JTAG Timing All Frequencies Parameter1,2 ID 1 2 Unit Min Max 0.001 22 MHz 45 — ns 22.
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Electrical characteristics Table 90. SPDIF Timing Parameters Timing Parameter Range Parameter Symbol Unit Min Max SPDIF_IN Skew: asynchronous inputs, no specs apply — — 0.7 ns SPDIF_OUT output (Load = 50pf) • Skew • Transition rising • Transition falling — — — — — — 1.5 24.2 31.3 ns SPDIF_OUT output (Load = 30pf) • Skew • Transition rising • Transition falling — — — — — — 1.5 13.6 18.0 ns Modulating Rx clock (SPDIF_SR_CLK) period srckp 40.0 — ns SPDIF_SR_CLK high period srckph 16.
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Electrical characteristics 4.10.15 UART I/O configuration and timing parameters 4.10.15.0.1 UART Transmitter The following figure depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit format. Table 91 lists the UART RS-232 serial mode transmit timing characteristics. UA1 UARTx_TX_DATA (output) Start Bit POSSIBLE PARITY BIT UA1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP BIT UA1 UA1 NEXT START BIT Figure 53.
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Electrical characteristics 4.10.15.0.3 UART IrDA Mode Timing The following subsections give the UART transmit and receive timings in IrDA mode. UART IrDA Mode Transmitter The following figure depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 93 lists the transmit timing characteristics. UA3 UA3 UA4 UA3 UA3 UARTx_TX_DATA (output) Start Bit Bit 0 Bit 1 Bit 3 Bit 2 Bit 4 Bit 5 Bit 6 POSSIBLE PARITY BIT Bit 7 STOP BIT Figure 55.
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Electrical characteristics 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0] × (OSR+1)). 4.10.16 USB 2.0 PHY Parameters 4.10.16.1 USB 2.0 PHY Transmitter specifications This section describes the transmitter specifications for USB2.0 PHY. 4.10.16.1.1 USB 2.0 PHY full-speed/low-speed transmitter specifications The following table lists the full-speed/low-speed (FS/LS) transmitter specifications for USB2.0 PHY. Table 95. USB 2.
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Electrical characteristics 4.10.16.2 USB 2.0 PHY high-speed transmitter specifications The following table lists the high-speed (HS) transmitter specifications for USB 2.0 PHY. Table 96. USB 2.
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Electrical characteristics Table 97. USB 2.
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Electrical characteristics 4.10.16.4 USB 2.0 PHY full-speed/high-speed terminations specification The following table lists the full-speed/low-speed (FS/LS) Terminations Specification of USB 2.0 PHY. Table 100. USB 2.0 PHY FS/LS terminations specification Symbol Min Typ Max Units Bus Pull-Up resistor on US Port in IDLE State 900 — 1575 Ω Bus Pull-Up resistor on US Port in ACTIVE State 1425 — 3090 Ω RPD Bus Pull-Down resistor on DS Port 14.25 — 24.
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Electrical characteristics 4.10.17.2 USB 3.0 PHY transmitter module Table 103. USB 3.
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Electrical characteristics Table 103. USB 3.0 PHY transmitter module electrical specifications (continued) Symbol Description Min Typ Max Unit TTX-IDLE-TO-DIFF-DATA Maximum time to transition to valid diff signaling after leaving Electrical Idle — — 8 ns VTX-CM-AC-PP Tx AC peak-peak common mode voltage (5.
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Electrical characteristics Table 105. PLL module electrical specifications Parameter Symbol Description Min Typ Max Units 19.2 19.2/24/25/26/38.4 38.4 MHz Input Reference Clock REF CLK Frequency REF CLK — — — 47 — 53 MHz REF CLK — 40 40/48/50/52/100 100 MHz REF CLK RJ Tolerance — Integrated jitter from 10 kHz to 16 MHz after applying appropriate PLL ref clock transfer function and the protocol JTF — — 0.
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Electrical characteristics 4.11 Analog-to-digital converter (ADC) The following table shows the ADC electrical specifications for VREFH=VDD_ADC_1P8. Table 106. ADC electrical specifications (VREFH=VDD_ADC_1P8) Symbol Description Min Typ1 Max Unit Notes VREFL — VREFH V — VADIN Input Voltage CADIN Input capacitance — 4.
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Electrical characteristics The following table shows the ADC electrical specifications for 1V≤VREFH
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Electrical characteristics The following figure shows a plot of the ADC sample time versus RAS. Figure 57. Sample time vs. RAS i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev.
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Boot mode configuration 5 Boot mode configuration This section provides information on boot mode configuration pins allocation and boot devices interfaces allocation. 5.1 Boot mode configuration pins The following table provides boot options, functionality, fuse values, and associated pins. Several input pins are also sampled at reset and can be used to override fuse values, depending on the value of FORCE_BOOT_FROM_FUSE.
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Boot mode configuration Table 109.
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Package information and contact assignments 6 Package information and contact assignments This section contains package information and contact assignments for the following package(s): • FCPBGA 21 x 21 mm, 0.8 mm pitch • FCPBGA 17 x 17 mm, 0.8 mm pitch 6.1 FCPBGA, 21 x 21 mm, 0.8 mm pitch This section includes the following information for the 21 x 21 mm, 0.8 mm pitch package: • Mechanical package drawing • Ball map • Contact assignments i.
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Package information and contact assignments 6.1.1 21 x 21 mm package case outline The following figure shows the top, bottom, and side views of the 21 x 21 mm package. Figure 58. 21 x 21 mm Package Top, Bottom, and Side Views i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev.
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Package information and contact assignments The following notes pertain to the preceding figure, “21 x 21 mm Package Top, Bottom, and Side Views.” Figure 59. Notes on 21 x 21 mm Package Top, Bottom, and Side Views i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev.
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Package information and contact assignments 6.1.2 21 x 21 mm, 0.8 mm pitch, ball map The following page shows the 21 x 21 mm, 0.8 mm pitch, ball map. i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev.
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Package information and functional contact assignments for FCPBGA, 21 x 21 mm, 0.
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Package information and contact assignments 6.1.3 21 x 21 mm power supplies and functional contact assignments The following table shows the power supplies contact assignments for the 21 × 21 mm package Table 110.
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Package information and contact assignments Table 110.
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Package information and contact assignments The following table shows functional contact assignments for the 21 × 21 mm package. Table 111. 21 x 21 mm functional contact assignments Reset Condition Ball Ball Name Ball Type Default Mode Power Domain Default Function Default Default Direction Pull U35 ADC_IN0 VDD_ADC_DIG_1P8 GPIO ALT0 ADMA.ADC.IN0 INPUT PD(50K) U33 ADC_IN1 VDD_ADC_DIG_1P8 GPIO ALT0 ADMA.ADC.IN1 INPUT PD(50K) V32 ADC_IN2 VDD_ADC_DIG_1P8 GPIO ALT0 ADMA.ADC.
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Package information and contact assignments Table 111. 21 x 21 mm functional contact assignments (continued) Reset Condition Ball Ball Name Ball Type Default Mode Power Domain Default Function Default Default Direction Pull D22 EMMC0_DATA7 VDD_EMMC0_VSELECT_1P8_3P3 FASTD ALT0 CONN.EMMC0.DATA7 INPUT PD(50K) H22 EMMC0_RESET_B VDD_EMMC0_VSELECT_1P8_3P3 GPIO ALT4 LSIO.GPIO4.IO18 INPUT PU(50K) F22 EMMC0_STROBE VDD_EMMC0_VSELECT_1P8_3P3 FASTD ALT0 CONN.EMMC0.
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Package information and contact assignments Table 111. 21 x 21 mm functional contact assignments (continued) Reset Condition Ball Ball Name Ball Type Default Mode Power Domain Default Function Default Default Direction Pull AH34 JTAG_TDI VDD_ANA1_1P8 TEST ALT0 SCU.JTAG.TDI INPUT PU(50K) AF32 JTAG_TDO VDD_ANA1_1P8 TEST ALT0 SCU.JTAG.TDO OUTPUT HiZ AG35 JTAG_TMS VDD_ANA1_1P8 TEST ALT0 SCU.JTAG.TMS INPUT PU(50K) AD28 JTAG_TRST_B VDD_ANA1_1P8 TEST ALT0 SCU.JTAG.
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Package information and contact assignments Table 111. 21 x 21 mm functional contact assignments (continued) Reset Condition Ball Ball Name Ball Type Default Mode Power Domain ALT0 Default Function MIPI_DSI0.I2C0.SDA Default Default Direction Pull AB28 MIPI_DSI0_I2C0_SDA VDD_MIPI_DSI_DIG_1P8_3P3 GPIO INPUT PU(50K) AM16 MIPI_DSI1_CLK_N VDD_MIPI_DSI1_1P8 DSI MIPI_DSI1.CKN Hi-Z AP16 MIPI_DSI1_CLK_P VDD_MIPI_DSI1_1P8 DSI MIPI_DSI1.
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Package information and contact assignments Table 111. 21 x 21 mm functional contact assignments (continued) Reset Condition Ball Ball Name Ball Type Default Mode Power Domain Default Function Default Default Direction Pull AJ13 QSPI0A_DATA2 VDD_QSPI0A_1P8_3P3 FASTD ALT0 LSIO.QSPI0A.DATA2 INPUT PD(50K) AH12 QSPI0A_DATA3 VDD_QSPI0A_1P8_3P3 FASTD ALT0 LSIO.QSPI0A.DATA3 INPUT PD(50K) AL11 QSPI0A_DQS VDD_QSPI0A_1P8_3P3 FASTD ALT0 LSIO.QSPI0A.
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Package information and contact assignments Table 111. 21 x 21 mm functional contact assignments (continued) Reset Condition Ball Ball Name Ball Type Default Mode Power Domain Default Function Default Default Direction Pull P30 SPI0_SCK VDD_SPI_SAI_1P8_3P3 GPIO ALT0 ADMA.SPI0.SCK INPUT PD(50K) P34 SPI0_SDI VDD_SPI_SAI_1P8_3P3 GPIO ALT0 ADMA.SPI0.SDI INPUT PD(50K) R31 SPI0_SDO VDD_SPI_SAI_1P8_3P3 GPIO ALT4 LSIO.GPIO1.
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Package information and contact assignments Table 111. 21 x 21 mm functional contact assignments (continued) Reset Condition Ball Ball Name Ball Type Default Mode Power Domain Default Default Direction Pull Default Function G15 USB_SS3_TC2 VDD_USB_3P3 GPIO ALT0 ADMA.I2C1.SDA INPUT PD(50K) C15 USB_SS3_TC3 VDD_USB_3P3 GPIO ALT0 ADMA.I2C1.SDA INPUT PD(50K) A15 USB_SS3_TX_N VDD_USB_SS3_LDO_1P0_CAP USB3 CONN.USB_SS3.TX_M_LN_0 B16 USB_SS3_TX_P VDD_USB_SS3_LDO_1P0_CAP USB3 CONN.
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Package information and contact assignments The following table shows DDR pin function. Table 112.
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Package information and contact assignments Table 112.
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Package information and contact assignments Table 112.
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Package information and contact assignments 6.2 FCPBGA, 17 x 17 mm, 0.8 mm pitch This section includes the following: • Mechanical package drawing • Ball map for case FCPBGA, 17 x 17 mm, 0.8 mm pitch • Contact assignments i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev.
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Package information and contact assignments 6.2.1 17 x 17 mm package case outline The following figure shows the top, bottom, and side views of the 17 x 17 mm package. Figure 60. 17 x 17 mm Package Top, Bottom, and Side Views i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev.
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Package information and contact assignments The following notes pertain to the preceding figure, “17 x 17 mm Package Top, Bottom, and Side Views.” Figure 61. Notes on 17 x 17 mm Package Top, Bottom, and Side Views i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev.
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Package information and contact assignments 6.2.2 17 x 17 mm, 0.8 mm pitch, ball map The following page shows the 17 x 17 mm, 0.8 mm pitch, ball map. i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev.
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Package information and functional contact assignments for FCPBGA, 17 x 17 mm, 0.
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Package information and contact assignments 6.2.3 17 x 17 mm power supplies and functional contact assignments The following table shows the power supplies contact assignments for the 17 x 17 mm package. Table 113.
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Package information and contact assignments Table 113.
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Package information and contact assignments The following table shows functional contact assignments for the 17 x 17 mm package. Table 114. 17 x 17 mm functional contact assignments Reset Condition Ball Ball Name Ball Type Default Mode Power Domain Default Function Default Direction Default Pull P24 ADC_IN0 VDD_ADC_DIG_1P8 GPIO ALT0 ADMA.ADC.IN0 Input PD(50K) N23 ADC_IN1 VDD_ADC_DIG_1P8 GPIO ALT0 ADMA.ADC.IN1 Input PD(50K) N27 ADC_IN2 VDD_ADC_DIG_1P8 GPIO ALT0 ADMA.ADC.
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Package information and contact assignments Table 114. 17 x 17 mm functional contact assignments (continued) Reset Condition Ball Ball Name Power Domain Ball Type Default Mode Default Function E3 DDR_DCF03 VDD_DDR_VDDQ DDR DRC.DCF03 K6 DDR_DCF04 VDD_DDR_VDDQ DDR DRC.DCF04 D4 DDR_DCF05 VDD_DDR_VDDQ DDR DRC.DCF05 B4 DDR_DCF07 VDD_DDR_VDDQ DDR DRC.DCF07 K2 DDR_DCF08 VDD_DDR_VDDQ DDR DRC.DCF08 L3 DDR_DCF09 VDD_DDR_VDDQ DDR DRC.DCF09 G1 DDR_DCF10 VDD_DDR_VDDQ DDR DRC.
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Package information and contact assignments Table 114. 17 x 17 mm functional contact assignments (continued) Reset Condition Ball Ball Name Ball Type Default Mode Power Domain Default Function Default Direction Default Pull N1 DDR_DQ02 VDD_DDR_VDDQ DDR DRC.DQ02 T2 DDR_DQ03 VDD_DDR_VDDQ DDR DRC.DQ03 Y2 DDR_DQ04 VDD_DDR_VDDQ DDR DRC.DQ04 AB2 DDR_DQ05 VDD_DDR_VDDQ DDR DRC.DQ05 AC1 DDR_DQ06 VDD_DDR_VDDQ DDR DRC.DQ06 AC3 DDR_DQ07 VDD_DDR_VDDQ DDR DRC.
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Package information and contact assignments Table 114. 17 x 17 mm functional contact assignments (continued) Reset Condition Ball Ball Name Ball Type Default Mode Power Domain VDD_EMMC0_VSELECT_1P8_3P3 FASTD Default Function Default Direction Default Pull ALT0 CONN.EMMC0.STROBE Input PD(50K) J17 EMMC0_STROBE A25 ENET0_MDC VDD_ENET_MDIO_1P8_3P3 GPIO ALT4 LSIO.GPIO5.IO11 Input PD(50K) J21 ENET0_MDIO VDD_ENET_MDIO_1P8_3P3 GPIO ALT0 CONN.ENET0.
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Package information and contact assignments Table 114. 17 x 17 mm functional contact assignments (continued) Reset Condition Ball Ball Name Ball Type Default Mode Power Domain Default Function Default Direction Default Pull U29 FLEXCAN1_TX VDD_CAN_UART_1P8_3P3 GPIO ALT4 LSIO.GPIO1.IO18 Input PD(50K) T28 FLEXCAN2_RX VDD_CAN_UART_1P8_3P3 GPIO ALT0 ADMA.FLEXCAN2.RX Input PD(50K) U27 FLEXCAN2_TX VDD_CAN_UART_1P8_3P3 GPIO ALT4 LSIO.GPIO1.
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Package information and contact assignments Table 114. 17 x 17 mm functional contact assignments (continued) Reset Condition Ball Ball Name Ball Type Default Mode Power Domain ALT0 Default Function Default Direction Default Pull MIPI_DSI0.I2C0.SDA Input PU(50K) V22 MIPI_DSI0_I2C0_SDA VDD_MIPI_CSI_DIG_1P8 GPIO AG9 MIPI_DSI1_CLK_N VDD_MIPI_DSI1_1P8 DSI MIPI_DSI1.CKN AJ9 MIPI_DSI1_CLK_P VDD_MIPI_DSI1_1P8 DSI MIPI_DSI1.CKP AF8 MIPI_DSI1_DATA0_N VDD_MIPI_DSI1_1P8 DSI MIPI_DSI1.
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Package information and contact assignments Table 114. 17 x 17 mm functional contact assignments (continued) Reset Condition Ball Ball Name Ball Type Default Mode Power Domain Default Function Default Direction Default Pull AJ5 QSPI0A_DATA0 VDD_QSPI0A_1P8_3P3 FASTD ALT0 LSIO.QSPI0A.DATA0 Input PD(50K) AH4 QSPI0A_DATA1 VDD_QSPI0A_1P8_3P3 FASTD ALT0 LSIO.QSPI0A.DATA1 Input PD(50K) AC9 QSPI0A_DATA2 VDD_QSPI0A_1P8_3P3 FASTD ALT0 LSIO.QSPI0A.
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Package information and contact assignments Table 114. 17 x 17 mm functional contact assignments (continued) Reset Condition Ball Ball Name Ball Type Default Mode Power Domain Default Function Default Direction Default Pull D26 SPI3_CS0 VDD_SPI_MCLK_UART_1P8_3P3 GPIO ALT0 ADMA.SPI3.CS0 Input PD(50K) F28 SPI3_CS1 VDD_SPI_MCLK_UART_1P8_3P3 GPIO ALT0 ADMA.SPI3.CS1 Input PD(50K) D28 SPI3_SCK VDD_SPI_MCLK_UART_1P8_3P3 GPIO ALT0 ADMA.SPI3.
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Package information and contact assignments The following table shows the DDR 17 x 17 mm pin function. Table 115. i.
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Package information and contact assignments Table 115. i.
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Release notes 7 Release notes This table provides release notes for the data sheet. Table 116. Data sheet release notes Rev. Number 0 Date Substantive Change(s) 11/2018 Initial release i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev.
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