Datasheet

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i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018

84 NXP Semiconductors

Package information and contact assignments

NAND_READY_B K20 NVCC_NAND GPIO ALT5 GPIO3.IO[16] Input PD (90 K)

NAND_WE_B K22 NVCC_NAND GPIO ALT5 GPIO3.IO[17] Input PD (90 K)

NAND_WP_B K21 NVCC_NAND GPIO ALT5 GPIO3.IO[18] Input PD (90 K)

ONOFF W21 NVCC_SNVS GPIO ALT0 snvsmix.ONOFF Input PU (27 K)

PCIE1_REF_PAD_

CLK_N

K24 PCIE1_VPH PHY — — — —

PCIE1_REF_PAD_

CLK_P

K25 PCIE1_VPH PHY — — — —

PCIE1_RESREF G25 PCIE1_VPH PHY — — — —

PCIE1_RXN_N H24 PCIE1_VPH PHY — — — —

PCIE1_RXN_P H25 PCIE1_VPH PHY — — — —

PCIE1_TXN_N J24 PCIE1_VPH PHY — — — —

PCIE1_TXN_P J25 PCIE1_VPH PHY — — — —

PCIE2_REF_PAD_

CLK_N

F24 PCIE2_VPH PHY — — — —

PCIE2_REF_PAD_

CLK_P

F25 PCIE2_VPH PHY — — — —

PCIE2_RESREF C25 PCIE2_VPH PHY — — — —

PCIE2_RXN_N D24 PCIE2_VPH PHY — — — —

PCIE2_RXN_P D25 PCIE2_VPH PHY — — — —

PCIE2_TXN_N E24 PCIE2_VPH PHY — — — —

PCIE2_TXN_P E25 PCIE2_VPH PHY — — — —

PMIC_ON_REQ V20 NVCC_SNVS GPIO ALT0 snvsmix.PMIC_ON_REQ Output Open-Drain

PU (27 K)

PMIC_STBY_REQ V21 NVCC_SNVS GPIO ALT0 ccmsrcgpcmix.PMIC_ST

BY_REQ

Output Low

POR_B W20 NVCC_SNVS GPIO ALT0 snvsmix.POR_B Input PU (27 K)

RTC V22 NVCC_SNVS GPIO ALT0 snvsmix.RTC Input PD (90 K)

RTC_RESET_B W19 NVCC_SNVS GPIO ALT0 snvsmix.RTC_POR_B Input PU (27 K)

SAI1_MCLK A3 NVCC_SAI1 GPIO ALT5 GPIO4.IO[20] Input PD (90 K)

SAI1_RXC K1 NVCC_SAI1 GPIO ALT5 GPIO4.IO[1] Input PD (90 K)

SAI1_RXD0

K2 NVCC_SAI1 GPIO ALT5 GPIO4.IO[2] Input PD (90 K)

Table 82. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued)

Ball name Ball Power group Ball type

Reset condition

Default

mode

(Reset

mode)

Default function

(Signal name)

Input/

Output

Value