Datasheet

i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
8 NXP Semiconductors
Modules list
2 Modules list
The i.MX 8M Dual / 8M QuadLite / 8M Quad processors contain a variety of digital and analog modules.
Table 3 describes these modules in alphabetical order.
Table 3. i.MX 8M Dual / 8M QuadLite / 8M Quad modules list
Block mnemonic Block name Brief description
APBH-DMA NAND Flash and BCH ECC
DMA Controller
DMA controller used for GPMI2 operation.
Arm Arm Platform The Arm Core Platform includes a quad Cortex-A53 core and a
Cortex-M4 core. The Cortex-A53 core includes associated
sub-blocks, such as the Level 2 Cache Controller, Snoop Control
Unit (SCU), General Interrupt Controller (GIC), private timers,
watchdog, and CoreSight debug modules. The Cortex-M4 core is
used as a customer microcontroller.
BCH Binary-BCH ECC Processor The BCH module provides up to 62-bit ECC encryption/decryption
for NAND Flash controller (GPMI)
CAAM Cryptographic accelerator and
assurance module
CAAM is a cryptographic accelerator and assurance module. CAAM
implements several encryption and hashing functions, a run-time
integrity checker, entropy source generator, and a Pseudo Random
Number Generator (PRNG). The PRNG is certifiable by the
Cryptographic Algorithm Validation Program (CAVP) of the National
Institute of Standards and Technology (NIST).
CAAM also implements a Secure Memory mechanism. In i.MX 8M
Dual / 8M QuadLite / 8M Quad processors, the secure memory
provided is 32 KB.
CCM
GPC
SRC
Clock Control Module, General
Power Controller, System Reset
Controller
These modules are responsible for clock and reset distribution in the
system, and also for the system power management.
CSU Central Security Unit The Central Security Unit (CSU) is responsible for setting
comprehensive security policy within the i.MX 8M Dual / 8M
QuadLite / 8M Quad platform.
CTI-0
CTI-1
CTI-2
CTI-3
CTI-4
Cross Trigger Interface Cross Trigger Interface (CTI) allows cross-triggering based on inputs
from masters attached to CTIs. The CTI module is internal to the
Cortex-A53 core platform.
DAP Debug Access Port The DAP provides real-time access for the debugger without halting
the core to access:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan chains.
DC Display Controller Dual display controller
DDRC Double Data Rate Controller The DDR Controller has the following features:
• Supports 32/16-bit LPDDR4-3200, DDR4-2400, and
DDR3L-1600
• Supports up to 8 Gbyte DDR memory space