Datasheet

Boot mode configuration
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
NXP Semiconductors 71
4.2 Boot device interface allocation
Table 80 lists the interfaces that can be used by the boot process in accordance with the specific Boot
mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation,
which are configured during boot when appropriate.
Table 80. Interface allocation during boot
Interface IP Instance Allocated Pads During Boot Comment
SPI ECSPI-1 ECSPI1_SCLK, ECSPI1_MOSI, ECSPI1_MISO,
ECSPI1_SS0
Using the chip-select pin
depends on the fuse “CS select
(SPI only)“.
SPI ECSPI-2 ECSPI2_SCLK, ECSPI2_MOSI, ECSPI2_MISO,
ECSPI2_SS0
Using the chip-select pin
depends on the fuse “CS select
(SPI only)“.
NAND Flash GPMI NAND_ALE, NAND_CE0_B, NAND_CLE,
NAND_DATA00, NAND_DATA01, NAND_DATA02,
NAND_DATA03, NAND_DATA04, NAND_DATA05,
NAND_DATA06, NAND_DATA07, NAND_DQS,
NAND_RE_B, NAND_READY_B, NAND_WE_B,
NAND_WP_B
8-bit, only CS0 is supported.
SD/MMC USDHC-1 GPIO1_IO03, GPIO1_IO06, GPIO1_IO07,
SD1_RESET_B, SD1_CLK, SD1_CMD,
SD1_STROBE, SD1_DATA0, SD1_DATA1,
SD1_DATA2, SD1_DATA3, SD1_DATA4, SD1_DATA5,
SD1_DATA6, SD1_DATA7
1, 4, or 8-bit
SD/MMC USDHC-2 GPIO1_IO04, GPIO1_IO08, GPIO1_IO07,
SD2_RESET_B, SD2_CD_B, SD2_WP, SD2_CLK,
SD2_CMD, SD2_DATA0, SD2_DATA1, SD2_DATA2,
SD2_DATA3
1 or 4-bit
QSPI QSPI NAND_ALE, NAND_CE0_B, NAND_CE1_B,
NAND_CE2_B, NAND_CE3_B, NAND_CLE,
NAND_DATA00, NAND_DATA01, NAND_DATA02,
NAND_DATA03, NAND_DATA04, NAND_DATA05,
NAND_DATA06, NAND_DATA07, NAND_DQS,
NAND_RE_B
For QuadSPI flash
USB USB_OTG PHY — —