Datasheet
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
70 NXP Semiconductors
Boot mode configuration
4 Boot mode configuration
This section provides information on Boot mode configuration pins allocation and boot devices interfaces
allocation.
4.1 Boot mode configuration pins
Table 79 provides boot options, functionality, fuse values, and associated pins. Several input pins are also
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an
unblown fuse). For detailed Boot mode options configured by the Boot mode pins, see the “System Boot,
Fusemap, and eFuse” chapter in the i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processor
Reference Manual (IMX8MDQLQRM).
Table 79. Fuses and associated pins used for boot
Pin
Direction
at Reset
eFuse name
State during reset
(POR_B
asserted)
State after reset
(POR_B
deasserted)
Details
BOOT_MODE0 Input N/A Input with 95 K pull down Input with 95 K pull down Boot mode
selection
BOOT_MODE1 Input N/A Input with 95 K pull down Input with 95 K pull down Boot mode
selection
SAI1_RXD0 Input BOOT_CFG[0] Input with 95 K pull down Input with 95 K pull down Boot options pin
value overrides
fuse settings for
BT_FUSE_SEL =
“0“. Signal
configuration as
fuse override input
at power up. These
are special I/O lines
that control the boot
configuration during
product
development. In
production, the boot
configuration can
be controlled by
fuses.
SAI1_RXD1 Input BOOT_CFG[1] Input with 95 K pull down Input with 95 K pull down
SAI1_RXD2 Input BOOT_CFG[2] Input with 95 K pull down Input with 95 K pull down
SAI1_RXD3 Input BOOT_CFG[3] Input with 95 K pull down Input with 95 K pull down
SAI1_RXD4 Input BOOT_CFG[4] Input with 95 K pull down Input with 95 K pull down
SAI1_RXD5 Input BOOT_CFG[5] Input with 95 K pull down Input with 95 K pull down
SAI1_RXD6 Input BOOT_CFG[6] Input with 95 K pull down Input with 95 K pull down
SAI1_RXD7 Input BOOT_CFG[7] Input with 95 K pull down Input with 95 K pull down
SAI1_TXD0 Input BOOT_CFG[8] Input with 95 K pull down Input with 95 K pull down
SAI1_TXD1 Input BOOT_CFG[9] Input with 95 K pull down Input with 95 K pull down
SAI1_TXD2 Input BOOT_CFG[10] Input with 95 K pull down Input with 95 K pull down
SAI1_TXD3 Input BOOT_CFG[11] Input with 95 K pull down Input with 95 K pull down
SAI1_TXD4 Input BOOT_CFG[12] Input with 95 K pull down Input with 95 K pull down
SAI1_TXD5 Input BOOT_CFG[13] Input with 95 K pull down Input with 95 K pull down
SAI1_TXD6 Input BOOT_CFG[14] Input with 95 K pull down Input with 95 K pull down
SAI1_TXD7 Input BOOT_CFG[15] Input with 95 K pull down Input with 95 K pull down