Datasheet

Electrical characteristics
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
NXP Semiconductors 67
3.9.14 USB PHY parameters
This section describes the USB-OTG PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision
3.0 OTG, USB Host with the amendments below (On-The-Go and Embedded Host Supplement to the USB
Revision 3.0 Specification is not applicable to Host port):
• USB ENGINEERING CHANGE NOTICE
— Title: 5V Short Circuit Withstand Requirement Change
— Applies to: Universal Serial Bus Specification, Revision 2.0
• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
• USB ENGINEERING CHANGE NOTICE
— Title: Pull-up/Pull-down resistors
— Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE
— Title: Suspend Current Limit Changes
— Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE
— Title: USB 2.0 Phase Locked SOFs
— Applies to: Universal Serial Bus Specification, Revision 2.0
• On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
— Revision 2.0, version 1.1a, July 27, 2010
• Battery Charging Specification (available from USB-IF)
— Revision 1.2, December 7, 2010
3.9.14.1 USB_OTG*_REXT reference resistor connection
The bias generation and impedance calibration process for the USB OTG PHYs requires connection of
reference resistors 200
 1% precision on each of USB_OTG1_REXT and USB_OTG2_REXT pads to
ground.
3.9.14.2 USB_OTG_CHD_B USB battery charger detection external pullup
resistor connection
The usage and external resistor connection for the USB_OTG_CHD_B pin are described in Table 5, and
Section 3.7.3, “USB battery charger detection driver impedance.”
3.9.15 USB 2.0 PHY parameters
USB 2.0 PHY parameters are compatible with USB 3.0 PHY. See Section 3.9.16, “USB 3.0 PHY
parameters for more detailed information.