Datasheet

Electrical characteristics
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
NXP Semiconductors 65
Figure 40. SPDIF_SR_CLK timing diagram
Figure 41. SPDIF_ST_CLK timing diagram
3.9.13 UART I/O configuration and timing parameters
3.9.13.1 UART RS-232 I/O configuration in different modes
The UART interfaces of the i.MX 8M Dual / 8M QuadLite / 8M Quad can serve both as DTE or DCE
device. This can be configured by the DCEDTE control bit (default 0—DCE mode). Table 68 shows the
UART I/O configuration based on the enabled mode.
3.9.13.2 UART RS-232 Serial mode timing
This section describes the electrical information of the UART module in the RS-232 mode.
Table 68. UART I/O configuration vs. mode
Port
DTE Mode DCE Mode
Direction Description Direction Description
UARTx_RTS_B Output UARTx_RTS_B from DTE to DCE Input UARTx_RTS_B from DTE to DCE
UARTx_CTS_B Input UARTx_CTS_B from DCE to DTE Output UARTx_CTS_B from DCE to DTE
UARTx_TX_ DATA Input Serial data from DCE to DTE Output Serial data from DCE to DTE
UARTx_RX _DATA Output Serial data from DTE to DCE Input Serial data from DTE to DCE
SPDIF_SR_CLK
(Output)
V
M
V
M
srckp
srckph
srckpl
SPDIF_ST_CLK
(Input)
V
M
V
M
stclkp
stclkph
stclkpl