Datasheet

i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
64 NXP Semiconductors
Electrical characteristics
Figure 39. SAI Timing — Slave Modes
3.9.12 SPDIF timing parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 67 and Figure 40 and Figure 41 show SPDIF timing parameters for the Sony/Philips Digital
Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.
Table 67. SPDIF timing parameters
Parameter Symbol
Timing Parameter Range
Unit
Min Max
SPDIF_IN Skew: asynchronous inputs, no specs apply — — 0.7 ns
SPDIF_OUT output (Load = 50 pf)
•Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
24.2
31.3
ns
SPDIF_OUT output (Load = 30 pf)
•Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
13.6
18.0
ns
Modulating Rx clock (SPDIF_SR_CLK) period srckp 40.0 — ns
SPDIF_SR_CLK high period srckph 16.0 — ns
SPDIF_SR_CLK low period srckpl 16.0 — ns
Modulating Tx clock (SPDIF_ST_CLK) period stclkp 40.0 — ns
SPDIF_ST_CLK high period stclkph 16.0 — ns
SPDIF_ST_CLK low period stclkpl 16.0 — ns