Datasheet

i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
62 NXP Semiconductors
Electrical characteristics
• For loopback DQS sampling, the data strobe is output to the DQS pad
together with the serial clock. The data strobe is looped back from DQS
pad and used to sample input data.
Figure 37. QuadSPI output/write timing (DDR mode)
NOTE
T
css
and T
csh
are configured by the QuadSPIx_FLSHCR register; the default value of 3 is shown on the
timing. See the i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processor Reference Manual
(IMX8MDQLQRM) for more details.
3.9.11 SAI/I2S switching specifications
This section provides the AC timings for the SAI in Master (clocks driven) and Slave (clocks input) modes.
All timings are given for non inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]
= 0) and non inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock
and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
Table 64. QuadSPI output/write timing (DDR mode)
Symbol Parameter
Value
Unit
Min Max
T
DVO
Output data valid time — (0.25 x T
SCLK
) + 2 ns
T
DHO
Output data hold time (0.25 x T
SCLK
) - 0.5 — ns
T
CK
SCK clock period 20 — ns
T
CSS
Chip select output setup time 3 — SCK cycle(s)
T
CSH
Chip select output hold time 3 — ns
Table 65. Master mode SAI timing
Num Characteristic Min Max Unit
S1 SAI_MCLK cycle time 20 — ns
S2 SAI_MCLK pulse width high/low 40% 60% MCLK period
S3 SAI_BCLK cycle time 40 — ns

7&66 7&.
7'92
7'+2
7'92
7'+2
7&6+
463,[B6&/.
463,[B&6
463,[B6,2