Datasheet

i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
60 NXP Semiconductors
Electrical characteristics
• For loopback DQS sampling, the data strobe is output to the DQS pad
together with the serial clock. The data strobe is looped back from DQS
pad and used to sample input data.
Figure 34. QuadSPI output/write timing (SDR mode)
NOTE
T
css
and T
csh
are configured by the QuadSPIx_FLSHCR register; the default
value of 3 is shown on the timing. See the i.MX 8M Dual / 8M QuadLite /
8M Quad Applications Processor Reference Manual (IMX8MDQLQRM)
for more details.
Table 61. QuadSPI output/write timing (SDR mode)
Symbol Parameter
Value
Unit
Min Max
T
DVO
Output data valid time — 2 ns
T
DHO
Output data hold time -0.5 — ns
T
CK
SCK clock period 10 — ns
T
CSS
Chip select output setup time 3 — ns
T
CSH
Chip select output hold time 3 — ns
7&66 7&.
7&6+
7'92
7'+2
7'92
7'+2
463,[B6&/.
463,[B&6
463,[B6,2