Datasheet

i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
58 NXP Semiconductors
Electrical characteristics
3.9.8 PCIe PHY parameters
The PCIe interface is designed to be compatible with PCIe specification Gen2 x1 lane and supports the
PCI Express 1.1/2.0 standard.
3.9.8.1 PCIE_REXT reference resistor connection
The impedance calibration process requires connection of reference resistor 4.7 k 1% precision resistor
on PCIE_REXT pads to ground. It is used for termination impedance calibration.
3.9.9 Pulse width modulator (PWM) timing parameters
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
pin.
Figure 31 depicts the timing of the PWM, and Table 58 lists the PWM timing parameters.
Figure 31. PWM timing
3.9.10 Quad SPI (QSPI) timing parameters
This section describes the electrical information for QSPI.
V
PIN(absmax)
2
Maximum pin voltage level -0.15 — 1.45 V
T
VPIN(absmax)
3
Maximum transient time above V
PIN(max)
or below V
PIN(min)
— — 20 ns
1
When the pad voltage is within the signal voltage range between V
GNDSH(min)
to V
OH
+ V
GNDSH(max)
and the Lane Module is
in LP receive mode.
2
This value includes ground shift.
3
The voltage overshoot and undershoot beyond the V
PIN
is only allowed during a single 20 ns window after any LP-0 to LP-1
transition or vice versa. For all other situations it must stay within the V
PIN
range.
Table 58. PWM output timing parameters
ID Parameter Min Max Unit
PWM Module Clock Frequency 0 ipg_clk (66 MHz) MHz
P1 PWM output pulse width high 15 — ns
P2 PWM output pulse width low 15 — ns
Table 57. MIPI input characteristics DC specifications (continued)
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