Datasheet
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
54 NXP Semiconductors
Electrical characteristics
For DDR Toggle mode, Figure 28 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid
window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI
samples NAND_DATA[7:0] at both the rising and falling edges of a delayed NAND_DQS signal, which
is provided by an internal DPLL. The delay value of this register can be controlled by the GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 8M Dual / 8M
QuadLite / 8M Quad Applications Processor Reference Manual [IMX8MDQLQRM]). Generally, the
typical delay value is equal to 0x7, which means a 1/4 clock cycle delay is expected. But if the board delay
is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay.
3.9.5 HDMI 2.0 Tx module timing parameters
See the following specifications:
• HDMI 2.0a specification (HDMI.org)
• DisplayPort 1.3 standard (VESA.org)
— DP supports 1.6 GHz (RBR), 2.7 GHz (HBR), and 5.4 GHz (HBR2) rates. Those rates are
managed in API (Host).
— RBR supports 1080p60 (RGB 8b), HBR supports 4kp30 (RGB 8b) and HBR2 supports 4kp60
(RGB 8b).
See bandwidth details below.
Effective bandwidth per rate with 4 lanes:
— RBR: 1.62 x 4 x 8 / 10 = 5.184 Gbps
— HBR: 2.7 x 4 x 8 / 10 = 8.64 Gbps
NF24 postamble delay tPOST POST_DELAY T +0.43 [see
note
2
]
—ns
NF28 Data write setup tDS
6
0.25 tCK - 0.32 — ns
NF29 Data write hold tDH
6
0.25 tCK - 0.79 — ns
NF30 NAND_DQS/NAND_DQ read setup skew tDQSQ
7
—3.18ns
NF31 NAND_DQS/NAND_DQ read hold skew tQHS
7
—3.27ns
1
The GPMI toggle mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these register’s settings. In the table, AS/DS/DH represents each of these settings.
2
AS minimum value can be 0, while DS/DH minimum value is 1.
3
T = tCK (GPMI clock period) -0.075 ns (half of maximum p-p jitter).
4
CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started
with enough time of ALE/CLE assertion to low level.
5
PRE_DELAY+1 (AS+DS)
6
Shown in Figure 29.
7
Shown in Figure 30.
Table 48. Toggle mode timing parameters
1
(continued)
ID Parameter Symbol
Timing
T = GPMI Clock Cycle
Unit
Min. Max.