Datasheet
Electrical characteristics
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
NXP Semiconductors 49
In EDO mode (Figure 23), NF16/NF17 are different from the definition in non-EDO mode (Figure 22).
They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical values for them
are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI samples
NAND_DATAxx at the rising edge of delayed NAND_RE_B provided by an internal DPLL. The delay
value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX 8M Dual /
8M QuadLite / 8M Quad Applications Processor Reference Manual [IMX8MDQLQRM]). The typical
value of this control register is 0x8 at 50 MT/s EDO mode. But if the board delay is big enough and cannot
be ignored, the delay value should be made larger to compensate the board delay.
3.9.4.2 Source synchronous mode AC timing (ONFI 2.x compatible)
Figure 25 to Figure 27 show the write and read timing of Source Synchronous mode.
Figure 25. Source Synchronous mode command and address timing diagram
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