Datasheet
Electrical characteristics
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
NXP Semiconductors 45
3.9.3.2 RGMII signal switching specifications
The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver
devices.
Figure 17. RGMII transmit signal timing diagram original
Table 45. RGMII signal switching specifications
1
1
The timings assume the following configuration:
DDR_SEL = (11)b
DSE (drive-strength) = (111)b
Symbol Description Min. Max. Unit
T
cyc
2
2
For 10 Mbps and 100 Mbps, T
cyc
will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.
Clock cycle duration 7.2 8.8 ns
T
skewT
3
3
For all versions of RGMII prior to 2.0; this implies that PC board design will require clocks to be routed such that an additional
trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100, the Max value
is unspecified.
Data to clock output skew at transmitter -500 500 ps
T
skewR
3
Data to clock input skew at receiver 1 2.6 ns
Duty_G
4
4
Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long
as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned
between.
Duty cycle for Gigabit 45 85 %
Duty_T
4
Duty cycle for 10/100T 40 90 %
Tr/Tf Rise/fall time (20–80%) — 0.98 ns
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