Datasheet

Electrical characteristics
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
NXP Semiconductors 43
3.9.2.5 SDR50/SDR104 AC timing
Figure 15 depicts the timing of SDR50/SDR104, and Table 43 lists the SDR50/SDR104 timing
characteristics.
Figure 15. SDR50/SDR104 timing
3.9.2.6 Bus operation condition for 3.3 V and 1.8 V signaling
Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50
mode is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2 and NVCC_SD3 supplies are
identical to those shown in Table 25, "GPIO DC parameters," on page 28.
Table 43. SDR50/SDR104 interface timing specification
ID Parameter Symbols Min Max Unit
Card Input Clock
SD1 Clock Frequency Period t
CLK
5—ns
SD2 Clock Low Time t
CL
0.46 x t
CLK
0.54 x t
CLK
ns
SD3 Clock High Time t
CH
0.46 x t
CLK
0.54 x t
CLK
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD4 uSDHC Output Delay t
OD
-3 1 ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)
SD5 uSDHC Output Delay t
OD
-1.6 1 ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in DDR50 (Reference to CLK)
SD6 uSDHC Input Setup Time t
ISU
2.4 — ns
SD7 uSDHC Input Hold Time t
IH
1.4 — ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)
1
1
Data window in SDR100 mode is variable.
SD8 uSDHC Output Data Window t
ODW
0.5 x t
CLK
—ns
SCK
8-bit output from uSDHC to eMMC
8-bit input from eMMC to uSDHC
SD8
SD7
SD6
SD4/SD5
SD2
SD3
SD1