Datasheet

i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
42 NXP Semiconductors
Electrical characteristics
3.9.2.4 HS200 Mode timing
Figure 14 depicts the timing of HS200 mode, and Table 42 lists the HS200 timing characteristics.
Figure 14. HS200 mode timing
iti
SD6
uSDHC input skew t
RQ
—0.45ns
SD7
uSDHC hold skew t
RQH
—0.45ns
Table 42. HS200 interface timing specification
ID Parameter Symbols Min Max Unit
Card Input Clock
SD1 Clock Frequency Period t
CLK
5—ns
SD2 Clock Low Time t
CL
0.3 x t
CLK
0.7 x t
CLK
ns
SD3 Clock High Time t
CH
0.3 x t
CLK
0.7 x t
CLK
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
SD5 uSDHC Output Delay t
OD
-1.6 1 ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
1
1
HS200 is for 8 bits while SDR104 is for 4 bits.
SD8 uSDHC Output Data Window t
ODW
0.5 x t
CLK
—ns
Table 41. HS400 interface timing specification (continued)
ID Parameter Symbols Min Max Unit
6&.
ELWRXWSXWIURPX6'+&WRH00&
ELWLQSXWIURPH00&WRX6'+&
6'
6'6'
6'
6'
6'