Datasheet

Electrical characteristics
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
NXP Semiconductors 41
3.9.2.3 HS400 DDR AC timing—eMMC5.0 only
Figure 13 depicts the timing of HS400 mode, and Table 41 lists the HS400 timing characteristics. Be
aware that only data is sampled on both edges of the clock (not applicable to CMD). The CMD
input/output timing for HS400 mode is the same as CMD input/output timing for SDR104 mode. Check
SD5, SD6, and SD7 parameters in Table 43 SDR50/SDR104 Interface Timing Specification for CMD
input/output timing for HS400 mode.
Figure 13. HS400 Mode timing
SD3 uSDHC Input Setup Time t
ISU
2.4 — ns
SD4 uSDHC Input Hold Time t
IH
1.3 — ns
Table 41. HS400 interface timing specification
ID Parameter Symbols Min Max Unit
Card Input Clock
SD1 Clock frequency f
PP
0 200 MHz
SD2 Clock low time t
CL
0.46 x t
CLK
0.54 x t
CLK
ns
SD3 Clock high time t
CH
0.46 x t
CLK
0.54 x t
CLK
ns
uSDHC Output/Card Inputs DAT (Reference to SCK)
SD4
Output skew from data of edge of SCK t
OSkew1
0.45 — ns
SD5
Output skew from edge of SCk to data t
OSkew2
0.45 — ns
uSDHC Input/Card Outputs DAT (Reference to Strobe)
Table 40. eMMC4.4/4.41 interface timing specification (continued)
ID Parameter Symbols Min Max Unit
6'
6'
6' 6'
6'
6&.
2XWSXWIURP
6WUREH
,QSXWIURP
X6'+&WRH00&
H00&WRX6'+&
'$7
'$7
'$7

'$7
'$7
'$7

6'
6'
6'
6'