Datasheet

i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
40 NXP Semiconductors
Electrical characteristics
3.9.2.2 eMMC4.4/4.41 (dual data rate) AC timing
Figure 12 depicts the timing of eMMC4.4/4.41. Table 40 lists the eMMC4.4/4.41 timing characteristics.
Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).
Figure 12. eMMC4.4/4.41 timing
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
SD7 uSDHC Input Setup Time t
ISU
2.5 — ns
SD8 uSDHC Input Hold Time
4
t
IH
1.5 — ns
1
In Low-Speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
2
In Normal (Full) -Speed mode for SD/SDIO card, clock frequency can be any value between 0 – 25 MHz. In High-speed mode,
clock frequency can be any value between 0 – 50 MHz.
3
In Normal (Full) -Speed mode for MMC card, clock frequency can be any value between 0 – 20 MHz. In High-speed mode,
clock frequency can be any value between 0 – 52 MHz.
4
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
Table 40. eMMC4.4/4.41 interface timing specification
ID Parameter Symbols Min Max Unit
Card Input Clock
SD1 Clock Frequency (eMMC4.4/4.41 DDR) f
PP
052MHz
SD1 Clock Frequency (SD3.0 DDR) f
PP
050MHz
uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD2 uSDHC Output Delay t
OD
2.7 6.9 ns
uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
Table 39. SD/eMMC4.3 interface timing specification (continued)
ID Parameter Symbols Min Max Unit
SD1
SD2
SD3
Output from eSDHCv3 to card
Input from card to eSDHCv3
SDx_DATA[7:0]
SDx_CLK
SD4
SD2
......
......
SDx_DATA[7:0]