Datasheet

i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
4 NXP Semiconductors
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction
NOTE
The actual feature set depends on the part numbers as described in Table 2.
Functions such as display and camera interfaces, and connectivity
interfaces, may not be enabled for specific part numbers.
System debug Arm CoreSight debug and trace architecture
TPIU to support off-chip real-time trace
ETF with 4 KB internal storage to provide trace buffering
Unified trace capability for Quad Cortex-A53 and Cortex-M4 CPUs
Cross Triggering Interface (CTI)
Support for 5-pin (JTAG) debug interface
1
Please contact the NXP sales and marketing team for order details on HDCP enable parts.
Table 1. Features (continued)
Subsystem Feature