Datasheet

Electrical characteristics
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
NXP Semiconductors 39
3.9.2 Ultra-high-speed SD/SDIO/MMC host interface (uSDHC) AC
timing
This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (single data
rate) timing, eMMC4.4/4.41 (dual data rate) timing and SDR104/50 (SD3.0) timing.
3.9.2.1 SD/eMMC4.3 (single data rate) AC timing
Figure 11 depicts the timing of SD/eMMC4.3, and Table 39 lists the SD/eMMC4.3 timing characteristics.
Figure 11. SD/eMMC4.3 timing
Table 39. SD/eMMC4.3 interface timing specification
ID Parameter Symbols Min Max Unit
Card Input Clock
SD1 Clock Frequency (Low Speed) f
PP
1
0 400 kHz
Clock Frequency (SD/SDIO Full Speed/High Speed) f
PP
2
0 25/50 MHz
Clock Frequency (MMC Full Speed/High Speed) f
PP
3
0 20/52 MHz
Clock Frequency (Identification Mode) f
OD
100 400 kHz
SD2 Clock Low Time t
WL
7—ns
SD3 Clock High Time t
WH
7—ns
SD4 Clock Rise Time t
TLH
—3ns
SD5 Clock Fall Time t
THL
—3ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD6 uSDHC Output Delay t
OD
6.6 3.6 ns
SD1
SD3
SD5
SD4
SD7
SDx_CLK
SD2
SD8
SD6
Output from uSDHC to card
Input from card to uSDHC
SDx_DATA[7:0]
SDx_DATA[7:0]