Datasheet

Electrical characteristics
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
NXP Semiconductors 37
3.9.1 ECSPI timing parameters
This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing
parameters for master and slave modes.
3.9.1.1 ECSPI Master mode timing
Figure 9 depicts the timing of ECSPI in master mode. Table 37 lists the ECSPI master mode timing
characteristics.
Figure 9. ECSPI Master mode timing diagram
Table 37. ECSPI Master mode timing parameters
ID Parameter Symbol Min Max Unit
CS1 ECSPIx_SCLK Cycle Time–Read
ECSPIx_SCLK Cycle Time–Write
t
clk
125
25
—ns
CS2 ECSPIx_SCLK High or Low Time–Read
ECSPIx_SCLK High or Low Time–Write
t
SW
62.5
12.5
—ns
CS3 ECSPIx_SCLK Rise or Fall
1
1
See specific I/O AC parameters Section 3.6, “I/O AC parameters.”
t
RISE/FALL
——ns
CS4 ECSPIx_SS_B pulse width t
CSLH
Half ECSPIx_SCLK period — ns
CS5 ECSPIx_SS_B Lead Time (CS setup time) t
SCS
Half ECSPIx_SCLK period - 4 — ns
CS6 ECSPIx_SS_B Lag Time (CS hold time) t
HCS
Half ECSPIx_SCLK period - 2 — ns
CS7 ECSPIx_MOSI Propagation Delay (C
LOAD
=20pF) t
PDmosi
-1 1 ns
CS8 ECSPIx_MISO Setup Time t
Smiso
14 — ns
CS9 ECSPIx_MISO Hold Time t
Hmiso
0—ns
CS10 RDY to ECSPIx_SS_B Time
2
2
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
t
SDRY
5—ns
CS7
CS2
CS2
CS4
CS6
CS5
CS8
CS9
ECSPIx_SCLK
ECSPIx_SS_B
ECSPIx_MOSI
ECSPIx_MISO
ECSPIx_RDY_B
CS10
CS3
CS3
CS1