Datasheet

i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
36 NXP Semiconductors
Electrical characteristics
3.8.1 Reset timings parameters
Figure 7 shows the reset timing and Table 35 lists the timing parameters.
Figure 7. Reset timing diagram
3.8.2 WDOG Reset timing parameters
Figure 8 shows the WDOG reset timing and Table 36 lists the timing parameters.
Figure 8. WDOGx_B timing diagram
NOTE
RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or
approximately 30 ms.
NOTE
WDOGx_B output signals (for each one of the Watchdog modules) do not
have dedicated pins, but are muxed out through the IOMUX. See the
IOMUXC chapter of the i.MX 8M Dual / 8M QuadLite / 8M Quad
Applications Processor Reference Manual (IMX8MDQLQRM) for detailed
information.
3.9 External peripheral interface parameters
The following subsections provide information on external peripheral interfaces.
Table 35. Reset timing parameters
ID Parameter Min Max Unit
CC1 Duration of POR_B to be qualified as valid. 1 —
RTC_XTALI cycle
Table 36. WDOGx_B timing parameters
ID Parameter Min Max Unit
CC3 Duration of WDOG1_B Assertion 1 —
RTC_XTALI cycle
POR_B
CC1
(Input)
WDOGx_B
CC3
(Output)