Datasheet

Electrical characteristics
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
NXP Semiconductors 35
3.7.1 DDR I/O output buffer impedance
Table 34 shows DDR I/O output buffer impedance of i.MX 8M Dual / 8M QuadLite / 8M Quad
processors.
Note:
1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.
2. Calibration is done against 240
 external reference resistor.
3. Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.
3.7.2 Differential I/O output buffer impedance
The Differential CCM interface is designed to be compatible with TIA/EIA 644-A standard. See, TIA/EIA
STANDARD 644-A, Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface
Circuits (2001) for details.
3.7.3 USB battery charger detection driver impedance
The USB_OTG1_CHD_B open-drain output pin can be used to signal to power management and
monitoring device results of USB Battery Charger detection routines for the USB_OTG1 PHY instance.
Use of this pin requires an external pullup resistor, for more information see Table 5.
3.8 System modules timing
This section contains the timing and electrical parameters for the modules in each i.MX 8M Dual / 8M
QuadLite / 8M Quad processor.
Table 34. DDR I/O output buffer impedance
Parameter Symbol
Test Conditions
DSE
(Drive Strength)
Typical
Unit
NVCC_DRAM = 1.35
V (DDR3L)
DDR_SEL = 11
NVCC_DRAM = 1.2 V
(DDR4)
NVCC_DRAM = 1.1 V
(LPDDR4)
DDR_SEL = 10
Output Driver
Impedance
Rdrv 000000 Hi-Z Hi-Z Hi-Z

000010 240 240 240
000110 120 120 120
001010 80 80 80
001110 60 60 60
011010 48 48 48
011110 40 40 40
111010 34 34 34