Datasheet

i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
30 NXP Semiconductors
Electrical characteristics
3.5.2.1 LPDDR4 mode I/O DC parameters
3.5.3 Differential I/O port (CLKx_P/N)
The clock I/O interface is designed to be compatible with TIA/EIA 644-A standard. See TIA/EIA
STANDARD 644-A, Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface
Circuits (2001), for details.
The CLK1_P/CLK1_N is input only, while CLK2_P/CLK2_N is output only.
3.6 I/O AC parameters
This section includes the AC parameters of the following I/O types:
• General Purpose I/O (GPIO)
• Double Data Rate I/O (DDR) for DDR3L/DDR4/LPDDR4 modes
• Differential I/O (CLKx)
The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 3 and
Figure 4.
Table 29. LPDDR4 I/O DC electrical parameters
Parameters Symbol
Test
Conditions
Min Max Unit
High-level output voltage VOH Ioh= -0.1 mA 0.9 x OVDD — V
Low-level output voltage VOL Iol= 0.1 mA — 0.1 x OVDD V
Input Reference Voltage Vref — 0.49 x OVDD 0.51 x OVDD V
DC High-Level input voltage Vih_DC — VRef + 0.100 OVDD V
DC Low-Level input voltage Vil_DC — OVSS VRef – 0.100 V
Differential Input Logic High Vih_diff — 0.26 See note
1
1
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot.
—
Differential Input Logic Low Vil_diff — See note -0.26 —
Pull-up/Pull-down Impedance Mismatch Mmpupd — –15 15 %
240 unit calibration resolution Rres — — 10

Keeper Circuit Resistance Rkeep — 110 175 K
Input current (no pull-up/down) Iin VI = 0, VI = OVDD -2.5 2.5 A