Datasheet

Electrical characteristics
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
NXP Semiconductors 29
3.5.2 DDR I/O DC electrical characteristics
The DDR I/O pads support LPDDR 4, DDR4, and DDR3L operational modes. The DDR Memory
Controller (DDRMC) is designed to be compatible with JEDEC-compliant SDRAMs.
DDRMC operation is contingent upon the board’s DDR design adherence to the DDR design and layout
requirements stated in the hardware development guide for the i.MX 8M Dual / 8M QuadLite / 8M Quad
application processor.
Table 26. DC input logic level
Characteristics Symbol Min Max Unit
DC input logic high
1
1
It is the relationship of the V
DDQ
of the driving device and the V
REF
of the receiving device that determines noise margins.
However, in the case of V
IH
(DC) max (that is, input overdrive), it is the V
DDQ
of the receiving device that is referenced.
V
IH(DC)
V
REF
+100 — mV
DC input logic low V
IL(DC)
—V
REF
–100
Table 27. Output DC current drive
Characteristics Symbol Min Max Unit
Output minimum source DC current
1
1
When DDS=[111] and without ZQ calibration.
I
OH
(DC) –4 — mA
Output minimum sink DC current I
OL
(DC) 4 — mA
DC output high voltage(I
OH
= –0.1mA)
,2
2
The values of V
OH
and V
OL
are valid only for 1.2 V range.
V
OH
0.9 x V
DDQ
—V
DC output low voltage(I
OL
= 0.1mA)
,
V
OL
— 0.1 x V
DDQ
V
Table 28. Input DC current
Characteristics Symbol Min Max Unit
High level input current
1,2
1
The values of V
OH
and V
OL
are valid only for 1.2 V range.
2
Driver Hi-Z and input power-down (PD=High)
I
IH
–40 40 A
Low level input current
,
I
IL
–40 40 A