Datasheet

i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
24 NXP Semiconductors
Electrical characteristics
3.2.1 Power-up sequence
The i.MX 8M Dual / 8M QuadLite / 8M Quad processors have the following power-up sequence
requirements:
• Turn on NVCC_SNVS
• Turn on VDD_SNVS
• RTC_RESET_B release
• Turn on VDD_SOC and VDDA_0P9
• Turn on VDD_ARM, VDD_GPU, VDD_VPU, and VDD_DRAM (no sequence between these
four rails)
• Turn on VDDA_1P8_XXX, VDDA_DRAM (no sequence between these rails)
• Turn on NVCC_XXX and NVCC_DRAM (no sequence between these rails)
• POR_B release (it should be asserted during the entire power up sequence)
If the GPU/VPU is not used during the ROM boot sequence, VDD_GPU/VDD_VPU can stay off to reduce
the power during boot, and then turned on by software afterwards.
During the chip power up, the power of the PCIe PHY, USB PHY, HDMI PHY, and MIPI PHY could stay
off. After chip power up, the power of these PHys should be turned on. If any of the PHY power are turned
on during the power up sequence, the POR_B can be released after the PHY power is stable.
3.2.2 Power-down sequence
The i.MX 8M Dual / 8M QuadLite / 8M Quad processors have the following power-down sequence
requirements:
• Turn off NVCC_SNVS and VDD_SNVS last
• Turn off VDD_SOC after the other power rails or at the same time as other rails
• No sequence for other power rails during power down
3.2.3 Power supplies usage
I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This
can cause internal latch-up and malfunctions due to reverse current flows. For information about the I/O
power supply of each pin, see “Power Rail” columns in the pin list tables of Section 5, “Package
information and contact assignments.”
Table 18 lists the modules in each power domain.
Table 18. The modules in the power domains
Power Domain Modules in the domain
VDD_ARM Arm A53
VDD_GPU GC7000L GPU
VDD_VPU G1 and G2 VPU