Datasheet

Electrical characteristics

i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018

NXP Semiconductors 23

PCIe PHY interface is compliant with PCIe Express GEN2.

3.2 Power supplies requirements and restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state

guidelines as described in this section to guarantee the reliable operation of the device. Any deviation

from these sequences may result in the following situations:

• Excessive current during power-up phase

• Prevention of the device from booting

• Irreversible damage to the processor (worst-case scenario)

TX Serial data output voltage (Differential, pk–pk) V

2.5 Gbps 800 — 1100 mVp–p

5.0 Gbps 600 — 900

PCIe Tx deterministic jitter < 1.5 MHz TRJ 2.5 Gbps 3 — — ps, rms

5.0 Gbps 3 — —

PCIe Tx deterministic jitter > 1.5 MHz TDJ 2.5 Gbps — — 20 ps, pk–pk

5.0 Gbps — — 10

RX Serial data input voltage (Differential pk–pk) V

2.5 Gbps 120 — 1200 mVp–p

5.0 Gbps 120 — 1200

Table 17. PCIe PHY reference clock timing requirements (vp is PIE_VP, 0.9 V power supply)

Symbol Parameter Min. Typ. Max. Unit Condition

FREF_OFFSET Reference clock frequency offset -300 — 30 ppm —

DJREF_CLK Reference clock cycle to cycle jitter — — 35 ps DJ across all frequencies

DCREF_CLK Duty cycle 40 — 60 % —

VCMREF_CLK Common mode input level 0 — vp V Differential inputs

VDREF_CLK Differential input swing -0.3 — — V

Differential inputs

VOLREF_CLK Single-ended input logic low -0.3 — -0.3 V If single-ended input is

used.

VOHREF_CLK Single-ended input logic high vp - 0.3 — vp + 0.3 V If single-ended input is

used.

SWREF_CLK Input edge rate — — — V/ns —

REF_CLK_SKEW Reference clock skew (±) — — 200 ps —

Table 16. PCIe PHY high-speed characteristics (continued)

High Speed I/O Characteristics

Description Symbol Speed Min. Typ. Max. Unit