Datasheet

i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 0, 01/2018
2 NXP Semiconductors
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction
Table 1. Features
Subsystem Feature
Arm Cortex-A53 MPCore platform Quad symmetric Cortex-A53 processors:
• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache
• Support L1 cache RAMs protection with parity/ECC
Support of 64-bit Armv8-A architecture:
• 1 MB unified L2 cache
• Support L2 cache RAMs protection with ECC
• Frequency of 1.5 GHz
Arm Cortex-M4 core platform 16 KB L1 Instruction Cache
16 KB L1 Data Cache
256 KB tightly coupled memory (TCM)
Connectivity Two PCI Express Gen2 interfaces
Two USB 3.0/2.0 controllers with integrated PHY interfaces
Two Ultra Secure Digital Host Controller (uSDHC) interfaces
One Gigabit Ethernet controller with support for EEE, Ethernet AVB, and IEEE 1588
Four Universal Asynchronous Receiver/Transmitter (UART) modules
Four I
2
C modules
Three SPI modules
External memory interface 32/16-bit DRAM interface: LPDDR4-3200, DDR4-2400, DDR3L-1600
8-bit NAND-Flash
eMMC 5.0 Flash
SPI NOR Flash
QuadSPI Flash with support for XIP
GPIO and pin multiplexing GPIO modules with interrupt capability
Input/output multiplexing controller (IOMUXC) to provide centralized pad control
On-chip memory Boot ROM (128 KB)
On-chip RAM (128 KB + 32 KB)
Power management Temperature sensor with programmable trip points
Flexible power domain partitioning with internal power switches to support efficient
power management