NXP Semiconductors Data Sheet: Technical Data Document Number: IMX8MDQLQIEC Rev. 0, 01/2018 MIMX8MQ7CVAHZAA MIMX8MD7CVAHZAA MIMX8MQ5CVAHZAA i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products MIMX8MQ6CVAHZAA MIMX8MD6CVAHZAA Package Information Plastic Package FBGA 17 x 17 mm, 0.65 mm pitch Ordering Information See Table 2 on page 6 1 i.MX 8M Dual / 8M QuadLite / 8M Quad introduction The i.
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction Table 1. Features Subsystem Arm Cortex-A53 MPCore platform Feature Quad symmetric Cortex-A53 processors: • 32 KB L1 Instruction Cache • 32 KB L1 Data Cache • Support L1 cache RAMs protection with parity/ECC Support of 64-bit Armv8-A architecture: • 1 MB unified L2 cache • Support L2 cache RAMs protection with ECC • Frequency of 1.
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction Table 1. Features (continued) Subsystem Multimedia Feature Video Processing Unit: • 4Kp60 HEVC/H.265 main, and main 10 decoder • 4Kp60 VP9 decoder • 4Kp30 AVC/H.264 decoder • 1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder Graphic Processing Unit: • 4 shader • 267 million triangles/sec • 1.6 Giga pixel/sec • 32 GFLOPs 32-bit or 64 GFLOPs 16-bit • Support OpenGL ES 1.1, 2.0, 3.0, 3.1, Open CL 1.
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction Table 1. Features (continued) Subsystem System debug Feature Arm CoreSight debug and trace architecture TPIU to support off-chip real-time trace ETF with 4 KB internal storage to provide trace buffering Unified trace capability for Quad Cortex-A53 and Cortex-M4 CPUs Cross Triggering Interface (CTI) Support for 5-pin (JTAG) debug interface 1 Please contact the NXP sales and marketing team for order details on HDCP enable parts.
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction 1.1 Block diagram Figure 1 shows the functional modules in the i.MX 8M Dual / 8M QuadLite / 8M Quad processor system.
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction 1.2 Ordering information Table 2 shows examples of orderable sample part numbers covered by this data sheet. This table does not include all possible orderable part numbers. If your desired part number is not listed in the table, or you have questions about available parts, contact your NXP representative. Table 2. Orderable part numbers Part number Options Cortex-A53 CPU speed grade Qualification tier Temperature Tj (C) MIMX8MQ7CVAHZAA 8M Quad 1.
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction M Qualification Level M Samples P Mass Production M Special S IMX8MQ @ + VN $$ A % Silicon Rev A Rev 1.0 A Fusing i.MX 8 Family Part # Series Description i.MX 8MQ Quad core i.MX 8MD Dual core A HDCP customer programmable * D HDCP NXP programmed C Frequency JZ 1.3 GHz HZ @ VPU decode + Dolby Vision + HDR10 + GPU 7 VPU decode + HDR10 + GPU 6 Package Type 5 17 x 17 mm, 0.
Modules list 2 Modules list The i.MX 8M Dual / 8M QuadLite / 8M Quad processors contain a variety of digital and analog modules. Table 3 describes these modules in alphabetical order. Table 3. i.MX 8M Dual / 8M QuadLite / 8M Quad modules list Block mnemonic Block name APBH-DMA NAND Flash and BCH ECC DMA Controller Arm Arm Platform The Arm Core Platform includes a quad Cortex-A53 core and a Cortex-M4 core.
Modules list Table 3. i.MX 8M Dual / 8M QuadLite / 8M Quad modules list (continued) Block mnemonic Block name eCSPI1 eCSPI2 eCSPI3 Configurable SPI EIM Brief description Full-duplex enhanced Synchronous Serial Interface, with data rate up to 52 Mbit/s. Configurable to support Master/Slave modes, four chip selects to support multiple peripherals.
Modules list Table 3. i.MX 8M Dual / 8M QuadLite / 8M Quad modules list (continued) Block mnemonic Block name Brief description IOMUXC IOMUX Control This module enables flexible I/O multiplexing. Each IO pad has a default as well as several alternate functions. The alternate functions are software configurable. LCDIF LCD interface The LCDIF is a general purpose display controller used to drive a wide range of display devices varying in size and capability.
Modules list Table 3. i.MX 8M Dual / 8M QuadLite / 8M Quad modules list (continued) Block mnemonic Block name Brief description SAI1 SAI2 SAI3 SAI4 SAI5 SAI6 Synchronous Audio Interface The SAI module provides a synchronous audio interface (SAI) that supports full duplex serial interfaces with frame synchronization, such as I2S, AC97, TDM, and codec/DSP interfaces. SDMA Smart Direct Memory Access The SDMA is a multichannel flexible DMA engine.
Modules list Table 3. i.MX 8M Dual / 8M QuadLite / 8M Quad modules list (continued) Block mnemonic Block name Brief description UART1 UART2 UART3 UART4 UART Interface Each of the UARTv2 modules supports the following serial data transmit/receive protocols and configurations: • 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none) • Programmable baud rates up to 4 Mbps. This is a higher max baud rate relative to the 1.875 MHz, which is stated by the TIA/EIA-232-F standard.
Electrical characteristics 3 Electrical characteristics This section provides the device and module-level electrical characteristics for the i.MX 8M Dual / 8M QuadLite / 8M Quad processors. 3.1 Chip-level conditions This section provides the device-level electrical characteristics for the IC. See Table 4 for a quick reference to the individual tables and sections. Table 4. i.
Electrical characteristics Table 5. Absolute maximum ratings (continued) Parameter description Symbol Min Max Unit Notes NVCC_JTAG, NVCCGPIO1, NVCC_ENT, NVCC_SD1, NVCC_SD2, NVCC_NAND, NVCC_SA1, NVCC_SAI2, NVCC_SAI3, NVCC_SAI5, NVCC_ECSPI, NVCC_I2C, NVCC_UART 0 3.6 V 1.8 V mode/3.3 V mode NVCC_SNVS 0 3.6 V 3.3 V mode only VDD_SNVS 0 0.99 V — USB1_VDD33, USB1_VPH, USB2_VDD33, USB2_VPH 0 3.63 V — USB_VBUS input detected USB1_VBUS, USB2_VBUS 0 5.
Electrical characteristics 2 Per JEDEC JESD51-2 with the single layer board horizontal. Thermal test board meets JEDEC specification for the specified package. 3 Per JEDEC JESD51-6 with the board horizontal. 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 3.1.
Electrical characteristics Table 7. Operating ranges (continued) Symbol Min Typ Max1 Unit Comment VDDA_1P8 1.62 1.8 1.98 V Power for internal analog blocks—must match the range of voltages that the rechargeable backup battery supports. VDDA_DRAM 1.71 1.8 1.89 V — VDD_SNVS 0.81 0.9 0.99 V — Supply for 25 MHz crystal VDD_1P8_XTAL_25M 1.6 1.8 1.98 V — Supply for 27 MHz crystal VDD_1P8_XTAL_27M 1.6 1.8 1.98 V — Temperature sensor VDD_1P8_TSENSOR 1.6 1.8 1.
Electrical characteristics Table 7. Operating ranges (continued) Parameter description GPIO supply voltages HDMI supply voltage MIPI supply voltage Voltage rails supplied from 1.8 V PHY Temperature sensor accuracy Fuse power Junction temperature, industrial 1 Symbol Min Typ Max1 Unit NVCC_JTAG, NVCC_SD1, NVCC_SD2, NVCC_NAND, NVCC_SAI1, NVCC_SAI2, NVCC_SAI3, NVCC_SAI5, NVCC_ECSPI, NVCC_I2C, NVCC_UART 1.65, 3.0 1.8, 3.3 1.95, 3.6 V — NVCC_ENET 1.65, 2.25 3.0 1.8, 2.5 3.3 1.95, 2.75 3.
Electrical characteristics 3.1.4 External clock sources A 25 MHz oscillator is used as the primary clock source for the PLLs to generate the clock for CPU, BUS, and high-speed interfaces. For fractional PLLs, the 25 MHz clock from the oscillator can be directly used as the PLL reference clock. A 27 MHz oscillator is used as the reference clock for HDMI PHY. Also it can be used as the alternative source for the fractional PLLs. A 32 kHz clock input pin is used as the RTC clock source.
Electrical characteristics Table 9. Maximum supply currents1 (continued) Power rail Max current Unit 0 to 6101 mA VDD_DRAM 600 to 8701 mA VDDA_0P9 50 mA VDDA_1P8 20 mA VDDA_DRAM 30 mA VDD_SNVS 2.5 mA 5 mA VDD_VPU NVCC_SNVS NVCC_ Imax = N x C x V x (0.5 x F) Where: N—Number of IO pins supplied by the power line C—Equivalent external capacitive load V—IO voltage (0.5 x F)—Data change rate. Up to 0.5 of the clock rate (F).
Electrical characteristics 3.1.6 Power modes The i.MX 8M Dual / 8M QuadLite / 8M Quad processor support the following power modes: • RUN Mode: All external power rails are on, CPU is active and running; other internal modules can be on/off based on application. • IDLE Mode: When there is no thread running and all high-speed devices are not active, the CPU can automatically enter this mode. The CPU can be in the power-gated state but with L2 data retained, DRAM and the bus clock are reduced.
Electrical characteristics 3.1.7 USB PHY Suspend current consumption 3.1.7.1 Low power Suspend Mode The VBUS Valid comparators and their associated bandgap circuits are enabled by default. Table 11 shows the USB interface current consumption in Suspend mode with default settings. Table 11. USB PHY current consumption in Suspend mode1 Current 1 USB1_VDD33 USB2_VDD33 154 154 Low Power Suspend is enabled by setting USBx_PORTSC1 [PHCD]=1 [Clock Disable (PLPSCD)]. 3.1.7.
Electrical characteristics Table 14. PCIe recommended operating conditions Parameter Description PCIE1_VP, PCIE2_VP Min Max Unit V Low Power Supply Voltage for PHY Core — 0.837 0.99 PCIE1_VPTX, PCIE2_VPTX PHY transmit supply — 0.837 0.99 PCIE1_VPH, PCIE2_VPH High Power Supply Voltage for PHY Core 1.8 1.674 1.98 3.3 3.069 3.
Electrical characteristics Table 16. PCIe PHY high-speed characteristics (continued) High Speed I/O Characteristics Description TX Serial data output voltage (Differential, pk–pk) PCIe Tx deterministic jitter < 1.5 MHz PCIe Tx deterministic jitter > 1.5 MHz RX Serial data input voltage (Differential pk–pk) Symbol Speed Min. Typ. Max. Unit VTX 2.5 Gbps 800 — 1100 mVp–p 5.0 Gbps 600 — 900 2.5 Gbps 3 — — 5.0 Gbps 3 — — 2.5 Gbps — — 20 5.0 Gbps — — 10 2.
Electrical characteristics 3.2.1 Power-up sequence The i.
Electrical characteristics Table 18. The modules in the power domains (continued) Power Domain Modules in the domain VDD_DRAM DRAM controller and PHY VDD_SNVS SNVS_LP VDD_SOC All the other modules 3.3 PLL electrical characteristics Table 19. PLL electrical parameters PLL type Parameter Value AUDIO_PLL1 Clock output range 650 MHz ~ 1.3 GHz Reference clock 25 MHz Lock time 50 s Jitter ±1% of output period, 50 ps Clock output range 650 MHz ~ 1.
Electrical characteristics Table 19. PLL electrical parameters (continued) PLL type Parameter Value ARM_PLL Clock output range 800 MHz ~1.6 GHz Reference clock 25 MHz Lock time 50 s Clock output range 400 MHz–800 MHz Reference clock 25 MHz Lock time 70 s Clock output range 800 MHz ~1.6 GHz Reference clock 25 MHz Lock time 50 s Clock output range 400 MHz ~ 800 MHz Reference clock 25 MHz Lock time 50 s DRAM_PLL GPU_PLL VPU_PLL 3.4 3.4.
Electrical characteristics 2 3 Electrical parameters are subject to change. Maximum current is observed during startup. After oscillation is stable, the current from HV supply comes down. Table 21 shows the transconductance specification of the oscillator (in mA/V). Table 21. Transconductance specification of oscillator GM_sel Min Max 10 25 111 Table 22 shows the input clock specifications. Table 22.
Electrical characteristics 3.5 I/O DC parameters This section includes the DC parameters of the following I/O types: • General Purpose I/O (GPIO) • Double Data Rate I/O (DDR) for LPDDR4, DDR4, and DDR3L modes • Differential I/O (CLKx) 3.5.1 General purpose I/O (GPIO) DC parameters Table 25 shows DC parameters for GPIO pads. The parameters in Table 25 are guaranteed per the operating ranges in Table 7, unless otherwise noted. Table 25.
Electrical characteristics 3.5.2 DDR I/O DC electrical characteristics The DDR I/O pads support LPDDR 4, DDR4, and DDR3L operational modes. The DDR Memory Controller (DDRMC) is designed to be compatible with JEDEC-compliant SDRAMs. DDRMC operation is contingent upon the board’s DDR design adherence to the DDR design and layout requirements stated in the hardware development guide for the i.MX 8M Dual / 8M QuadLite / 8M Quad application processor. Table 26.
Electrical characteristics 3.5.2.1 LPDDR4 mode I/O DC parameters Table 29. LPDDR4 I/O DC electrical parameters Symbol Test Conditions Min Max Unit High-level output voltage VOH Ioh= -0.1 mA 0.9 x OVDD — V Low-level output voltage VOL Iol= 0.1 mA — 0.1 x OVDD V Input Reference Voltage Vref — 0.49 x OVDD 0.51 x OVDD V DC High-Level input voltage Vih_DC — VRef + 0.100 OVDD V DC Low-Level input voltage Vil_DC — OVSS VRef – 0.
Electrical characteristics From Output Under Test Test Point CL CL includes package, probe and fixture capacitance Figure 3. Load circuit for output 80% 80% 20% Output (at pad) tf tr OVDD 20% 0V Figure 4. Output transition time waveform 3.6.1 General purpose I/O AC parameters This section presents the I/O AC parameters for GPIO in different modes. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the IOMUXC control registers. Table 30.
Electrical characteristics Table 31. Output cell delay time for fixed load (continued) Simulated Cell Delay A PAD (ns) Parameter VDD = 1.62 V, T = 125°C VDD = 2.97 V, T = 125°C dse[2:0] fsel[1:0] 111 00 111 11 Driver Type CL = 15 pF CL = 15 pF 7 x Slow Slew 2.9 3.1 7 x Fast Slew 1.8 2.3 Table 32. Maximum frequency of operation for input Maximum frequency (MHz) 3.6.2 VDD = 1.8 V, CL = 15 pF, fast — VDD = 3.
Electrical characteristics Table 33 shows the AC parameters for clock I/O. Table 33.
Electrical characteristics OVDD PMOS (Rpu) Ztl W, L = 20 inches ipp_do pad predriver Cload = 1p NMOS (Rpd) OVSS U,(V) Vin (do) VDD t,(ns) 0 U,(V) Vout (pad) OVDD Vref2 Vref1 Vref t,(ns) 0 Rpu = Vovdd - Vref1 x Ztl Vref1 Rpd = Vref2 x Ztl Vovdd - Vref2 Figure 6. Impedance matching load for measurement i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev.
Electrical characteristics 3.7.1 DDR I/O output buffer impedance Table 34 shows DDR I/O output buffer impedance of i.MX 8M Dual / 8M QuadLite / 8M Quad processors. Table 34. DDR I/O output buffer impedance Typical Parameter Output Driver Impedance Symbol Rdrv Test Conditions DSE (Drive Strength) NVCC_DRAM = 1.35 V (DDR3L) DDR_SEL = 11 NVCC_DRAM = 1.2 V (DDR4) NVCC_DRAM = 1.
Electrical characteristics 3.8.1 Reset timings parameters Figure 7 shows the reset timing and Table 35 lists the timing parameters. POR_B (Input) CC1 Figure 7. Reset timing diagram Table 35. Reset timing parameters ID CC1 3.8.2 Parameter Min Max Unit 1 — RTC_XTALI cycle Duration of POR_B to be qualified as valid. WDOG Reset timing parameters Figure 8 shows the WDOG reset timing and Table 36 lists the timing parameters. WDOGx_B (Output) CC3 Figure 8. WDOGx_B timing diagram Table 36.
Electrical characteristics 3.9.1 ECSPI timing parameters This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing parameters for master and slave modes. 3.9.1.1 ECSPI Master mode timing Figure 9 depicts the timing of ECSPI in master mode. Table 37 lists the ECSPI master mode timing characteristics. ECSPIx_RDY_B ECSPIx_SS_B CS10 CS2 CS3 CS1 CS5 CS6 CS4 ECSPIx_SCLK CS7 CS3 CS2 ECSPIx_MOSI CS8 CS9 ECSPIx_MISO Figure 9.
Electrical characteristics 3.9.1.2 ECSPI Slave mode timing Figure 10 depicts the timing of ECSPI in Slave mode. Table 38 lists the ECSPI Slave mode timing characteristics. ECSPIx_SS_B CS2 CS1 CS5 CS6 CS4 ECSPIx_SCLK CS2 CS9 ECSPIx_MISO CS7 CS8 ECSPIx_MOSI Figure 10. ECSPI Slave mode timing diagram Table 38.
Electrical characteristics 3.9.2 Ultra-high-speed SD/SDIO/MMC host interface (uSDHC) AC timing This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (single data rate) timing, eMMC4.4/4.41 (dual data rate) timing and SDR104/50 (SD3.0) timing. 3.9.2.1 SD/eMMC4.3 (single data rate) AC timing Figure 11 depicts the timing of SD/eMMC4.3, and Table 39 lists the SD/eMMC4.3 timing characteristics.
Electrical characteristics Table 39. SD/eMMC4.3 interface timing specification (continued) ID Parameter Symbols Min Max Unit uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK) SD7 uSDHC Input Setup Time SD8 4 uSDHC Input Hold Time tISU 2.5 — ns tIH 1.5 — ns 1 In Low-Speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. In Normal (Full) -Speed mode for SD/SDIO card, clock frequency can be any value between 0 – 25 MHz.
Electrical characteristics Table 40. eMMC4.4/4.41 interface timing specification (continued) ID Parameter Symbols Min Max Unit SD3 uSDHC Input Setup Time tISU 2.4 — ns SD4 uSDHC Input Hold Time tIH 1.3 — ns 3.9.2.3 HS400 DDR AC timing—eMMC5.0 only Figure 13 depicts the timing of HS400 mode, and Table 41 lists the HS400 timing characteristics. Be aware that only data is sampled on both edges of the clock (not applicable to CMD).
Electrical characteristics Table 41. HS400 interface timing specification (continued) ID Parameter Symbols Min Max Unit SD6 uSDHC input skew tRQ — 0.45 ns SD7 uSDHC hold skew tRQH — 0.45 ns 3.9.2.4 HS200 Mode timing Figure 14 depicts the timing of HS200 mode, and Table 42 lists the HS200 timing characteristics. 6' 6' 6' 6&. 6' 6' ELW RXWSXW IURP X6'+& WR H00& ELW LQSXW IURP H00& WR X6'+& 6' Figure 14. HS200 mode timing iti Table 42.
Electrical characteristics 3.9.2.5 SDR50/SDR104 AC timing Figure 15 depicts the timing of SDR50/SDR104, and Table 43 lists the SDR50/SDR104 timing characteristics. SD1 SD2 SD3 SCK SD4/SD5 8-bit output from uSDHC to eMMC SD6 SD7 8-bit input from eMMC to uSDHC SD8 Figure 15. SDR50/SDR104 timing Table 43. SDR50/SDR104 interface timing specification ID Parameter Symbols Min Max Unit 5 — ns Card Input Clock SD1 Clock Frequency Period tCLK SD2 Clock Low Time tCL 0.46 x tCLK 0.
Electrical characteristics 3.9.3 Ethernet controller (ENET) AC electrical specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 3.9.3.1 RMII mode timing In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference clock. ENET_RX_EN is used as the ENET_RX_EN in RMII.
Electrical characteristics 3.9.3.2 RGMII signal switching specifications The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver devices. Table 45. RGMII signal switching specifications1 Symbol Tcyc2 Description Clock cycle duration Min. Max. Unit 7.2 8.8 ns -500 500 ps TskewT3 Data to clock output skew at transmitter TskewR3 Data to clock input skew at receiver 1 2.
Electrical characteristics 2'-))?28# AT TRANSMITTER 4SKEW4 2'-))?28$N N TO 2'-))?28?#4, 28$6 28%22 4SKEW2 2'-))?28# AT RECEIVER Figure 18. RGMII receive signal timing diagram original 2'-))?28# SOURCE OF DATA )NTERNAL DELAY 4SETUP 4 4 HOLD 4 4 SETUP 2 4 HOLD 2 2'-))?28$N N TO 2'-))?28?#4, 28$6 28%22 2'-))?28# AT RECEIVER Figure 19. RGMII receive signal timing diagram with internal delay 3.9.4 General-purpose media interface (GPMI) timing The GPMI controller of the i.
Electrical characteristics .!.$?#,% E&ϯ .!.$?#% ?" E&Ϯ E&ϭ .!.$?7%?" E&ϱ E&ϰ E&ϲ .!.$?!,% E&ϳ E&ϴ E&ϵ ŽŵŵĂŶĚ .!.$?$!4!XX Figure 20. Command Latch cycle timing diagram E&ϭ .!.$?#,% E&ϯ .!.$?#% ?" E&ϭϬ .!.$?7%?" E&ϱ .!.$?!,% E&ϭϭ E&ϳ E&ϲ E&ϴ E E ͺ d dždž E&ϵ ĚĚƌĞƐƐ Figure 21. Address Latch cycle timing diagram E&ϭ .!.$?#,% .!.$?#% ?" E&ϯ E&ϭϬ E&ϱ .!.$?7%?" E&ϲ .!.$?!,% E&ϳ E&ϵ E&ϴ .!.
Electrical characteristics .!.$?#,% .!.$?#% ?" E&ϭϰ E&ϭϯ .!.$?2%?" .!.$?2%!$9?" E&ϭϱ E&ϭϮ E&ϭϳ E&ϭϲ E E ͺ d dždž ĂƚĂ ĨƌŽŵ E& Figure 24. Read Data Latch cycle timing diagram (EDO mode) Table 46. Asynchronous mode timing parameters1 ID Parameter Timing T = GPMI Clock Cycle Symbol Unit Min.
Electrical characteristics In EDO mode (Figure 23), NF16/NF17 are different from the definition in non-EDO mode (Figure 22). They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical values for them are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI samples NAND_DATAxx at the rising edge of delayed NAND_RE_B provided by an internal DPLL. The delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.
Electrical characteristics .!.$?#% ?" 1) 1) 1) .!.$?#,% 1) 1) 1) 1) 1) .!.$?!,% 1) 1) 1$1'B:( 5(B% 1) .!.$?#,+ 1) 1) .!.$?$13 .!.$?$13 2XWSXW HQDEOH 1) 1) .!.$?$1; = 1) 1) .!.$?$1; = 2XWSXW HQDEOH Figure 26. Source Synchronous mode data write timing diagram .!.$?#%?" 1) 1) 1) 1) .!.$?#,% 1$1'B$/( .!.$?7% 2% 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) .!.$?#,+ .!.$?$13 .!.$?$13 /UTPUT ENABLE .!.$?$!4!; = .!.
Electrical characteristics .!.$?$13 E&ϯϬ .!.$?$!4!; = Ϭ E&ϯϬ ϭ Ϯ E&ϯϭ ϯ E&ϯϭ Figure 28. NAND_DQS/NAND_DQ read valid window Table 47. Source Synchronous mode timing parameters1 ID Parameter Symbol Timing T = GPMI Clock Cycle Min. NF18 NAND_CE0_B access time NF19 NAND_CE0_B hold time tCE tCH Unit Max. CE_DELAY T - 0.79 [see note 2] 0.5 tCK - 0.63 [see note2] ns ns NF20 Command/address NAND_DATAxx setup time tCAS 0.5 tCK - 0.
Electrical characteristics 3.9.4.3 3.9.4.3.1 ONFI NV-DDR2 mode (ONFI 3.2 compatible) Command and address timing ONFI 3.2 mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing. See Section 3.9.4.1, “Asynchronous mode AC timing (ONFI 1.0 compatible),” for details. 3.9.4.3.2 Read and write timing ONFI 3.2 mode read and write timing is the same as Toggle mode AC timing. See Section 3.9.4.4, “Toggle mode AC Timing,” for details. 3.9.4.4 3.9.4.4.
Electrical characteristics DEV?CLK .!.$?#%X?" .& .!.$?#,% .!.$?!,% .!.$?7%?" T #+ .& T #+ .& .!.$?2%?" T #+ T #+ T #+ .!.$?$13 .!.$?$!4!; = Figure 30. Toggle mode data read timing Table 48. Toggle mode timing parameters1 ID Parameter Symbol Timing T = GPMI Clock Cycle Min. Unit Max. NF1 NAND_CLE setup time tCLS (AS + DS) T - 0.12 [see note2s,3] NF2 NAND_CLE hold time tCLH DH T - 0.72 [see note2] NF3 NAND_CE0_B setup time tCS (AS + DS) T - 0.
Electrical characteristics Table 48. Toggle mode timing parameters1 (continued) ID Parameter Timing T = GPMI Clock Cycle Symbol Unit Min. Max. NF24 postamble delay tPOST POST_DELAY T +0.43 [see note2] — ns NF28 Data write setup tDS6 0.25 tCK - 0.32 — ns 0.25 tCK - 0.79 — ns — 3.18 ns — 3.
Electrical characteristics — HBR2: 1.62 x4 x 8 / 10 = 17.28 Gbps Bandwidth required per resolution (CEA-861-F): — 1920 x 1080 (24 b/px) 60 fps: 3.56 Gbps — 3840 x 2160 (24 b/px) 30 fps: 7.13 Gbps — 3840 x 2160 (24 b/px) 30 fps: 14.26 Gbps Embedded DisplayPort 1.4 standard (VESA.org) — eDP link rates: R216 (2.16 Gbps), R243 (2.43 Gbps), R324 (3.24 Gbps), and R432 (4.32 Gbps) — Fast Link Training is also supported • DDC link requires external pull-up resistors to be connected to a 5 V supply.
Electrical characteristics Table 51. MIPI high-speed transmitter AC specifications Symbol Min Typ Max Unit VCMTX(HF) Common-level variations above 450 MHz — — 8 mVRMS VCMTX(LF) Common-level variation between 50-450 MHz — — 10 mVPEAK 160 — 0.3 UI ps Min Typ Max Unit tR and 1 Parameter tF1 Rise Time and Fall Time (20% to 80%) UI is the long-term average unit interval. 3.9.7.2 MIPI LP-TX specifications Table 52.
Electrical characteristics 5 When the output voltage is between 15% and 85% of the fully settled LP signal levels. Measured as average across any 50 mV segment of the output signal transition. 7 This value represents a corner point in a piecewise linear curve. 6 3.9.7.3 MIPI LP-RX specifications Table 54. MIPI low power receiver DC specifications Symbol Parameter Min Typ Max Unit 880 — 1.
Electrical characteristics Table 57. MIPI input characteristics DC specifications (continued) VPIN(absmax)2 Maximum pin voltage level TVPIN(absmax)3 Maximum transient time above VPIN(max) or below VPIN(min) -0.15 — 1.45 V — — 20 ns 1 When the pad voltage is within the signal voltage range between VGNDSH(min) to VOH + VGNDSH(max) and the Lane Module is in LP receive mode. 2 This value includes ground shift.
Electrical characteristics Measurement is with a load of 35 pF on SCK and SIO pins and an input slew rate of 1 V/ns. 3.9.10.1 SDR Mode 463,[B6&/. 7,6 7,+ 7,6 7,+ 463,[B'$7$> @ Figure 32. QuadSPI input/read timing (SDR mode with internal sampling) Table 59. QuadSPI input timing (SDR mode with internal sampling) Value Symbol Parameter Unit TIS Setup time for incoming data TIH Hold time requirement for incoming data Min Max 8.67 — ns 0 — ns 463,[B6&/.
Electrical characteristics • For loopback DQS sampling, the data strobe is output to the DQS pad together with the serial clock. The data strobe is looped back from DQS pad and used to sample input data. 463,[B6&/. 7&66 7&6+ 7&. 463,[B&6 7'92 7'92 463,[B6,2 7'+2 7'+2 Figure 34. QuadSPI output/write timing (SDR mode) Table 61. QuadSPI output/write timing (SDR mode) Value Symbol Parameter Unit Min Max TDVO Output data valid time — 2 ns TDHO Output data hold time -0.
Electrical characteristics 3.9.10.2 DDR mode 463,[B6&/. 7,6 7,+ 7,6 7,+ 463,[B'$7$> @ Figure 35. QuadSPI input/read timing (DDR mode with internal sampling) Table 62. QuadSPI input/read timing (DDR mode with internal sampling) Value Symbol Parameter Unit TIS Setup time for incoming data TIH Hold time requirement for incoming data Min Max 8.67 — ns 0 — ns 463,[B6&/. 463,[B'$7$> @ 7,6 7,+ 7,6 7,+ 463,[B'46 Figure 36.
Electrical characteristics • For loopback DQS sampling, the data strobe is output to the DQS pad together with the serial clock. The data strobe is looped back from DQS pad and used to sample input data. 463,[B6&/. 7&66 7&. 7&6+ 463,[B&6 7'92 7'92 463,[B6,2 7'+2 7'+2 Figure 37. QuadSPI output/write timing (DDR mode) Table 64. QuadSPI output/write timing (DDR mode) Value Symbol Parameter Unit Min Max TDVO Output data valid time — (0.25 x TSCLK) + 2 ns TDHO Output data hold time (0.
Electrical characteristics Table 65. Master mode SAI timing (continued) Num Characteristic Min Max Unit S4 SAI_BCLK pulse width high/low 40% 60% BCLK period S5 SAI_BCLK to SAI_FS output valid — 15 ns S6 SAI_BCLK to SAI_FS output invalid 0 — ns S7 SAI_BCLK to SAI_TXD valid — 15 ns S8 SAI_BCLK to SAI_TXD invalid 0 — ns S9 SAI_RXD/SAI_FS input setup before SAI_BCLK 15 — ns S10 SAI_RXD/SAI_FS input hold after SAI_BCLK 0 — ns Figure 38. SAI timing—Master modes Table 66.
Electrical characteristics Figure 39. SAI Timing — Slave Modes 3.9.12 SPDIF timing parameters The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Electrical characteristics srckp srckpl SPDIF_SR_CLK srckph VM VM (Output) Figure 40. SPDIF_SR_CLK timing diagram stclkp stclkpl SPDIF_ST_CLK stclkph VM VM (Input) Figure 41. SPDIF_ST_CLK timing diagram 3.9.13 3.9.13.1 UART I/O configuration and timing parameters UART RS-232 I/O configuration in different modes The UART interfaces of the i.MX 8M Dual / 8M QuadLite / 8M Quad can serve both as DTE or DCE device. This can be configured by the DCEDTE control bit (default 0—DCE mode).
Electrical characteristics 3.9.13.2.1 UART transmitter Figure 42 depicts the transmit timing of UART in the RS-232 Serial mode, with 8 data bit/1 stop bit format. Table 69 lists the UART RS-232 Serial mode transmit timing characteristics. UA1 Start Bit UARTx_TX_DATA (output) Possible Parity Bit UA1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Par Bit STOP BIT Bit 7 Next Start Bit UA1 UA1 Figure 42. UART RS-232 Serial mode transmit timing diagram Table 69.
Electrical characteristics 3.9.14 USB PHY parameters This section describes the USB-OTG PHY parameters. The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision 3.0 OTG, USB Host with the amendments below (On-The-Go and Embedded Host Supplement to the USB Revision 3.0 Specification is not applicable to Host port): • USB ENGINEERING CHANGE NOTICE — Title: 5V Short Circuit Withstand Requirement Change — Applies to: Universal Serial Bus Specification, Revision 2.
Electrical characteristics 3.9.16 USB 3.0 PHY parameters This section describes the electrical information about USB 3.0 PHY. Table 71 shows the USB 3.0 PHY junction temperature. Table 71. USB 3.0 PHY junction temperature Min Max -40 C 125 C Table 72 shows the USB 3.0 PHY power dissipation of SuperSpeed 5-Gbps operation. Table 72. USB 3.
Electrical characteristics Table 75. USB power pin supplies (continued) Pin Name Description Value USB1/2_VPTX PHY transmit supply 0.9 V (+22.2%, -7%) USB1/2_VDD33 High supply for high-speed operation IO 3.3 V (+10%, -7%) USB1/2_VPH High supply for SuperSpeed operation IO 3.3 V (+10%, -7%) Table 76 shows the external component values. Table 76.
Boot mode configuration 4 Boot mode configuration This section provides information on Boot mode configuration pins allocation and boot devices interfaces allocation. 4.1 Boot mode configuration pins Table 79 provides boot options, functionality, fuse values, and associated pins. Several input pins are also sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
Boot mode configuration 4.2 Boot device interface allocation Table 80 lists the interfaces that can be used by the boot process in accordance with the specific Boot mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation, which are configured during boot when appropriate. Table 80.
Package information and contact assignments 5 Package information and contact assignments This section includes the contact assignment information and mechanical package drawing. 5.1 5.1.1 17 x 17 mm package information 17 x 17 mm, 0.65 mm pitch, ball matrix Figure 44 shows the top, bottom, and side views of the 17 × 17 mm BGA package. i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev.
Package information and contact assignments Figure 44. 17 x 17 mm BGA, package top, bottom, and side Views i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev.
Package information and contact assignments 5.1.2 17 x 17 mm supplies contact assignments and functional contact assignments Table 81 shows supplies contact assignments for the 17 x 17 mm package. Table 81. i.
Package information and contact assignments Table 81. i.
Package information and contact assignments Table 81. i.
Package information and contact assignments Table 82 shows an alpha-sorted list of functional contact assignments for the 17 x 17 mm package. Table 82. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments Reset condition2 Ball name Ball Power group Ball type1 Default mode (Reset mode) Default function (Signal name) Input/ Output Value BOOT_MODE0 W6 NVCC_JTAG GPIO ALT0 ccmsrcgpcmix.BOOT_M ODE[0] Input PD (90 K) BOOT_MODE1 V6 NVCC_JTAG GPIO ALT0 ccmsrcgpcmix.
Package information and contact assignments Table 82. i.
Package information and contact assignments Table 82. i.
Package information and contact assignments Table 82. i.
Package information and contact assignments Table 82. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued) Reset condition2 Ball name Ball Power group Ball type1 Default mode (Reset mode) Default function (Signal name) Input/ Output Value GPIO1_IO04 P5 NVCC_GPIO1 GPIO ALT0 GPIO1.IO[4] Input PD (90 K) GPIO1_IO054 P7 NVCC_GPIO1 GPIO ALT0 GPIO1.IO[5] Input PU (27 K) GPIO1_IO06 N5 NVCC_GPIO1 GPIO ALT0 GPIO1.
Package information and contact assignments Table 82. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued) Reset condition2 Ball name Ball Power group Ball type1 Default mode (Reset mode) Default function (Signal name) Input/ Output Value I2C1_SDA E8 NVCC_I2C GPIO ALT5 GPIO5.IO[15] Input PD (90 K) I2C2_SCL G7 NVCC_I2C GPIO ALT5 GPIO5.IO[16] Input PD (90 K) I2C2_SDA F7 NVCC_I2C GPIO ALT5 GPIO5.
Package information and contact assignments Table 82. i.
Package information and contact assignments Table 82. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued) Reset condition2 Ball name Ball Power group Ball type1 Default mode (Reset mode) Default function (Signal name) Input/ Output Value NAND_READY_B K20 NVCC_NAND GPIO ALT5 GPIO3.IO[16] Input PD (90 K) NAND_WE_B K22 NVCC_NAND GPIO ALT5 GPIO3.IO[17] Input PD (90 K) NAND_WP_B K21 NVCC_NAND GPIO ALT5 GPIO3.
Package information and contact assignments Table 82. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued) Reset condition2 Ball name Ball Power group Ball type1 Default mode (Reset mode) Default function (Signal name) Input/ Output Value SAI1_RXD15 L2 NVCC_SAI1 GPIO ALT5 GPIO4.IO[3] Input PD (90 K) SAI1_RXD25 H2 NVCC_SAI1 GPIO ALT5 GPIO4.IO[4] Input PD (90 K) 5 SAI1_RXD3 J2 NVCC_SAI1 GPIO ALT5 GPIO4.
Package information and contact assignments Table 82. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued) Reset condition2 Ball name Ball Power group Ball type1 Default mode (Reset mode) Default function (Signal name) Input/ Output Value SAI3_TXD C3 NVCC_SAI3 GPIO ALT5 GPIO5.IO[1] Input PD (90 K) SAI3_TXFS G3 NVCC_SAI3 GPIO ALT5 GPIO4.IO[31] Input PD (90 K) SAI5_MCLK K4 NVCC_SAI5 GPIO ALT5 GPIO3.
Package information and contact assignments Table 82. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued) Reset condition2 Ball name Ball Power group Ball type1 Default mode (Reset mode) Default function (Signal name) Input/ Output Value SPDIF_EXT_CLK E6 NVCC_SAI3 GPIO ALT5 GPIO5.IO[5] Input PD (90 K) SPDIF_RX G6 NVCC_SAI3 GPIO ALT5 GPIO5.IO[4] Input PD (90 K) SPDIF_TX F6 NVCC_SAI3 GPIO ALT5 GPIO5.
Package information and contact assignments Table 82. i.
SAI1_RXD3 VSS SAI2_RXFS SAI2_TXC GPIO1_IO15 NVCC_SAI2 VSS VDD_GPU VDD_GPU VSS VSS VSS VSS VDD_ARM VDD_ARM VSS VSS VSS SAI1_RXD0 NVCC_SAI1 SAI5_MCLK SAI5_RXD3 NXP Semiconductors GPIO1_IO13 GPIO1_IO14 VSS VDD_GPU VDD_GPU VSS VDD_SOC VSSA_FPLL_ARM VDDA_1P8_FPLL-ARM VDD_ARM VDD_ARM VSS VSS NAND_RE_B PCIE2_TXN_P PCIE1_REF_PAD_CLK_P PCIE1_TXN_P PCIE1_RXN_P PCIE1_RESREF PCIE2_REF_PAD_CLK_P VSS PCIE2_TXN_N PCIE_VPTX PCIE2_REF_PAD_CLK_N VSS PCIE_VPTX VSS VSS 24 PCIE2_RXN_P PCIE2_RXN_N V
HDMI_REFCLK_P HDMI_TX_M_LN_0 HDMI_AVDDIO HDMI_REXT GPIO1_IO02 NVCC_GPIO1 NVCC_GPIO1 VSS VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC EFUS_VQPS VDD_SNVS ENET_TD2 ENET_TD0 ENET_TD1 SD2_RESET_B CLK1_P SD1_RESET_B SD1_DATA6 JTAG_TCK GPIO1_IO00 GPIO1_IO01 VDD_SOC VSS VSS VSS VSS VSS VSSA_SPLL_DRAM VDDA_1P8_SPLL_DRAM VDDA_1P8_TSENSOR VDD_SOC NVCC_ENET ENET_TXC ENET_RXC ENET_RX_CTL CLK2_P CLK1_N SD1_STROBE SD1_DATA7 SD1_DATA2 SD1_DATA0 SD1_DATA1 SD1_CLK SD1_CMD NV
DRAM_DQ23 VSS NVCC_DRAM DRAM_DQ24 DRAM_DQS3_P DRAM_DM3 DRAM_DQ29 NVCC_DRAM VSS DRAM_AC35 VSS DRAM_AC26 DRAM_DQS2_N DRAM_DQS2_P NVCC_DARM VSS DRAM_DQS3_N NVCC_DRAM DRAM_AC28 NVCC_DRAM DRAM_AC23 DRAM_AC34 DRAM_AC38 DRAM_AC36 NXP Semiconductors DRAM_AC07 DRAM_AC14 NVCC_DRAM VSS DRAM_DQ13 DRAM_DM1 DRAM_DQS1_P DRAM_DQ08 NVCC_DRAM VSS DRAM_DQ07 DRAM_AC15 DRAM_AC00 NVCC_DRAM DRAM_AC03 VSS NVCC_DRAM DRAM_DQS1_N VSS NVCC_DRAM DRAM_DQS0_P DRAM_DQS0_N VSS VDDA_1P8_XTAL_25M XTALI_27M XTALO_2
Package information and contact assignments 5.
Package information and contact assignments Table 84.
Package information and contact assignments Table 84.
Revision history 6 Revision history Table 85 provides a revision history for this data sheet. Table 85. Revision history Rev. number Rev. 0 Date Substantive change(s) 01/2018 • Initial version i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev.
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