Datasheet

MC33411A/B
35
MOTOROLA RF/IF DEVICE DATA
MCU Serial Interface
The MCU Serial Interface is a 3–wire interface, consisting
of a Clock line, an Enable line, and a bi–directional Data line.
The interface is always active, i.e., it cannot be powered
down as all other sections of the MC33411 are disabled and
enabled through this interface.
After the device power–up (or whenever a reset condition
is required), the MCU should perform the following steps:
1. Initialize the Data line to a high impedance state.
2. Initialize the Clock line to a logic low.
3. Initialize the Enable line to a logic low.
4. Pulse the Clock line a minimum of once (RZ format)
while leaving the Enable line continuously low. This
places the SPI port into a known condition.
5. Load all registers with their desired initial values.
The clock (Return–to–Zero format) must be supplied to the
MC33411 at Pin 11 to write or read data, and can be any
frequency up to 2.0 MHz. The clock need not be present
when data is not being transferred. The Enable line must be
low when data is not being transferred.
Internally there are 7 data registers, 24–bits each, addressed
with 4–bits ranging from $h1 to $h7 (see Tables 9 and 10).
Register 5, bits 23–12 are read–only bits, while all other register
bits are Read/Write. All unused/unimplemented bits are
reserved for Motorola use only. The contents of the 7 registers
can be read out at any time. All bits are written in, or read out,
on the clock’s positive transition. The write and read operations
are as follows:
Figure 52. Writing Data to the MC33411
Clock
Data
Enable
123 24
4–Bit Address
24–Bit Data from MCU
MSB LSB
Latch Address Latch Data
a. Write Operation:
– To write data to the MC33411, the following sequence is
required (see Figure 52):
6. The Enable line is taken high.
7. Five bits are entered:
– The first bit must be a 0 to indicate a Write operation.
– The next four bits identify the register address
(0001–0111). The MSB is entered first.
8. The Enable line is taken low. At this transition, the address
is latched in and decoded.
9. The Enable line is maintained low while the data bits are
clocked in. The MSB is entered first, and the LSB last. If
24–bits are written to a register which has less than 24 active
bits (e.g., register 6), the unassigned bits are to be 0.
10. After the last bit is entered, the Enable line is to be taken
high and then low. The falling edge of this pulse latches in
the just entered data. The clock line must be at a logic low
and must not transition in either direction during this Enable
pulse.
11.The Enable line must then be kept low until the next
communication.
Note: If less than 24 bits are to be written to a data register,
it is not necessary to enter the full 24 bits, as long as they are
all lower order bits. For example, if bits 0–6 of a register are to
be updated, they can be entered as 7 bits with 7 clock cycles
in step 4 above. However, if this procedure is used, a minimum
of 4 bits, with 4 clock pulses, must be entered.
ARCHIVE INFORMATION
ARCHIVE INFORMATION
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eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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