Datasheet
MC33411A/B
31
MOTOROLA RF/IF DEVICE DATA
Loop Filter Characteristics
Let’s consider the following discussion on loop filters. The
fundamental loop characteristics, such as capture range,
loop bandwidth, lock–up time, and transient response are
controlled externally by loop filtering.
Figure 46 is the general model for a Phase Lock Loop
(PLL).
Phase
Detector (K
pd
)
Filter
(K
f
)
VCO
(K
o
)
fo
Divider
(K
n
)
fi
Figure 46. PLL Model
Where:
K
pd
= Phase Detector Gain Constant
K
f
= Loop Filter Transfer Function
K
o
= VCO Gain Constant
K
n
= Divide Ratio (N)
fi = Input frequency
fo = Output frequency
fo/N = Feedback frequency divided by N
From control theory the loop transfer function can be
represented as follows:
A
+
K
pd
K
f
K
o
K
n
Open loop gain
K
pd
can be either expressed as being 200 µA/4π or
800 µA/4π. More details about performance of different type
PLL loops, refer to Motorola application note AN535.
The loop filter can take the form of a simple low pass filter.
A current output, type 2 filter will be used in this discussion
since it has the advantage of improved step response,
velocity, and acceleration.
The type 2 low pass filter discussed here is represented as
follows:
From
Phase
Detector
To VCO
R2
C2C1
Figure 47. Loop Filter
with Additional Integrating Element
From Figure 47, capacitor C1 forms an additional
integrator, providing the type 2 response, and filters the
discrete current steps from the phase detector output. The
function of the additional components R2 and C2 is to create
a pole and a zero (together with C1) around the 0 dB point of
the open loop gain. This will create sufficient phase margin
for stable loop operation.
In Figure 48, the open loop gain and the phase is
displayed in the form of a Bode plot. Since there are two
integrating functions in the loop, originating from the loopfilter
and the VCO gain, the open loop gain response follows a
second order slope (–40 dB/dec) creating a phase of –180
degrees at the lower and higher frequencies. The filter
characteristic needs to be determined such that it is adding a
pole and a zero around the 0 dB point to guarantee sufficient
phase margin in this design (Qp in Figure 48).
Phase
Figure 48. Bode Plot of Gain and
Phase in Open Loop Condition
A
,
O
pe
n Loo
p
G
a
in
ω
p
Open Loop Gain
Q
p
–180
–90
0
0
The open loop gain including the filter response can be
expressed as:
A
openloop
+
K
pd
K
o
(1
)
j
w
(R2C2))
j
w
K
n
ǒ
j
w
ǒ
1
)
j
w
ǒ
R2C1C2
C1
)
C2
Ǔ
Ǔ
Ǔ
(4)
The two time constants creating the pole and the zero in
the Bode plot can now be defined as:
T1
+
R2C1C2
C1
)
C2
T2
+
R2C2 (5)
By substituting equation (5) into (4), it follows:
A
openloop
+
ǒ
K
pd
K
o
T1
w
2
C1K
n
T2
Ǔ
ǒ
1
)
j
w
T2
1
)
j
w
T1
Ǔ
(6)
The phase margin (phase + 180) is thus determined by:
Q
p
+
arctan
(
w
T2
)
–arctan
(
w
T1
)
(7)
At ω=ω
p
, the derivative of the phase margin may be set to
zero in order to assure maximum phase margin occurs at ω
p
(see also Figure 48). This provides an expression for ω
p
:
dQ
p
d
w
+
0
+
T2
1
)
(
w
T2
)
2
–
T1
1
)
(
w
T1
)
2
(8)
w
+
w
p
+
1
T2T1
Ǹ
(9)
Or rewritten:
T1
+
1
w
p
2
T2
(10)
By substituting into equation (7), solve for T2:
T2
+
tan
ǒ
Q
p
2
)
p
4
Ǔ
w
p
(11)
ARCHIVE INFORMATION
ARCHIVE INFORMATION
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...