Datasheet

MC33411A/B
26
MOTOROLA RF/IF DEVICE DATA
Reference Oscillator/MCU Clk Out
The reference oscillator provides the frequency basis for
the three PLLs, the switched capacitor filters, and the MCU
clock output. The source for the reference clock can be a
crystal in the range of 4.0 to 18.25 MHz connected to Pins
15 & 16, or it can be an external source connected to F
ref
In
(Pin 15). The reference frequency is directed to:
a. A programmable 12–bit counter (register bits 4/11–0) to
provide the reference frequency for the three PLLs. The
12–bit counter is to be set such that, in conjunction with the
programmable counters within each PLL, the proper
frequencies can be produced by each VCO.
b. A programmable 6–bit counter (register bits 4/17–12),
followed by a ÷2 stage, to set the frequency for the switched
capacitor filters to 165 kHz, or as close to that as possible.
c. A programmable 3–bit counter (register bits 7/16–14)
which provides the MCU clock output (see Tables 5 and 6).
A representation of the reference oscillator is given by
Figures 35 and 36.
Figure 35. Reference Oscillator Schematic
Reference Oscillator
R
PI
C
PI
R
PO
C
PO
Gm
F
ref
In F
ref
Out
Xtal
C
2
C
1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 36. Reference Oscillator
Input and Output Impedance
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Input Impedance (R
PI
// C
PI
)
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
11.6 k // 2.9 pF
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Output Impedance (R
PO
// C
PO
)
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
4.5 k // 2.5 pF
Figures 37 and 38 show a typical gain/phase response of
the oscillator. Load capacitance (C
L
), equivalent series
resistance (ESR), and even supply voltage will have an effect
on the oscillator response as shown in Figures 39 and 40. It
should be noted that optimum performance is achieved when
C1 equals C2 (C1/C2 = 1).
Figure 41 represents the ESR versus crystal load
capacitance for the reference oscillator. This relationship was
defined by using a 6.0 dB minimum loop gain margin at 3.6 V.
This is considered the minimum gain margin to guarantee
oscillator start–up.
Oscillator start–up is also significantly affected by the
crystal load capacitance selection. In Figure 39, the
relationship between crystal load capacitance and ESR can
be seen. The lower the load capacitance the better the
performance.
Given the desired crystal load capacitance, C1 and C2
can be determined from Figure 42. It should also be pointed
out that current consumption increases when C1 C2.
Be careful not to overdrive the crystal. This could cause a
noise problem. An external series resistor on the crystal
output can be added to reduce the drive level, if necessary.
ARCHIVE INFORMATION
ARCHIVE INFORMATION
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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