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MC33411A/B

MOTOROLA RF/IF DEVICE DATA

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Table 1. Tx Gain Adjust Programming (Register 7)

Gain Control

Bit #9

Gain Control

Bit #8

Gain Control

Bit #7

Gain Control

Bit #6

Gain Control

Bit #5

Gain

Ctl #

Gain/Attenuation

Amount

<6 –9.0 dB

0 0 1 1 0 6 –9.0 dB

0 0 1 1 1 7 –8.0 dB

0 1 0 0 0 8 –7.0 dB

0 1 0 0 1 9 –6.0 dB

0 1 0 1 0 10 –5.0 dB

0 1 0 1 1 11 –4.0 dB

0 1 1 0 0 12 –3.0 dB

0 1 1 0 1 13 –2.0 dB

0 1 1 1 0 14 –1.0 dB

0 1 1 1 1 15 0 dB

1 0 0 0 0 16 1.0 dB

1 0 0 0 1 17 2.0 dB

1 0 0 1 0 18 3.0 dB

1 0 0 1 1 19 4.0 dB

1 0 1 0 0 20 5.0 dB

1 0 1 0 1 21 6.0 dB

1 0 1 1 0 22 7.0 dB

1 0 1 1 1 23 8.0 dB

1 1 0 0 0 24 9.0 dB

1 1 0 0 1 25 10 dB

– – – – – >25 10 dB

Transmit Speech Processing System

This portion of the audio path goes from ”Tx Audio” to ”Tx

Out”. The gain of the microphone amplifier is set with external

resistors to receive the audio from the microphone hybrid or

any other audio source. The MCO output has rail–to–rail

capability. The ”Tx Audio” pin will be ac–coupled. The audio

transmit signal path includes automatic level control (ALC)

(also referred to as the Compressor), Tx mute, limiter, filters,

and Tx gain adjust. The ALC provides ”soft” limiting to the

output signal swing as the input voltage slowly increases.

With this technique the gain is slightly lowered to help reduce

distortion of the audio signal. The limiter section provides

hard limiting due to rapidly changing singal levels, or

transients. The ALC, TX mute, and limiter functions can be

enabled or disabled vis the MCU serial interface. The Tx gain

adjust can also be remotely controlled to set different desired

signal levels.

The adjustable gain stage provides 20 levels of gain in

1.0 dB increments. It is controlled with bits 7/9–5 as shown in

Table 1. The effect of the gain setting under various

ALC/Limiter On/Off settings is shown in Figure 9.

The Low–Pass Filter before the gain stage is a switched

capacitor filter with a corner frequency at 3.7 kHz. This

frequency is dependent upon the SCF clock, nominaly set to

165 kHz and is directly proportional to the SCF clock. The

filter response for inband, ripple, wideband, as well as phase

and group delay, are shown in Figures 10 through 14.

The mute switch at Pin 18 will mute a minimum of 60 dB.

Bit 6/2 controls the mute. The limiter can be disabled by

programming a logic 1 into 6/5.

The compressor with ALC transfer characteristic is shown

in Figure 15. The ALC gain is controlled by bits 6/11–12. If

both bits are programmed to a logic 0, the ALC gain is set to

5.0 dB. If bit 6/11 is set to a logic 1, the ALC gain will be set to

10 dB, whereas if bit 6/12 is set to a logic 1 the ALC gain will be

25 dB. The ALC function may be disabled by programming a

logic 1 into bit 6/6.

The compressor low maximum gain can be set with bit 6/8.

Programming this bit to a logic 0 sets the maximum gain to

23 dB. A lower maximum gain, nominally 13.5 dB, is

achieved by programming the bit to a logic 1. The entire

compressor can be bypassed (i.e., 0 dB) by programming bit

6/4 to a logic 1.

Figures 16 through 22 describe the characteristics of the

compressor, ALC, and limiter.

ARCHIVE INFORMATION

eescale S

emiconduct

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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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