Datasheet
52 NXP Semiconductors
10XS3435
10 Additional documentation
10.1 Thermal addendum (Rev 2.0)
10.1.1 Introduction
This thermal addendum is provided as a supplement to the 10XS3435 technical data
sheet. The addendum provides thermal performance information that may be critical in
the design and development of system applications. All electrical, application and
packaging information is provided in the data sheet.
10.1.2 Package and thermal considerations
This 10XS3435 is a dual die package. There are two heat sources in the package
independently heating with P
1
and P
2
. This results in two junction temperatures, T
J1
and
T
J2
, and a thermal resistance matrix with R
θJAmn
.
For m, n = 1, R
θJA11
is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P
1
.
For m = 1, n = 2, R
θJA12
is the thermal resistance from Junction 1 to the reference
temperature while heat source 2 is heating with P
2
. This applies to R
θJ21
and R
θJ22
,
respectively.
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This
methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were
obtained by measurement and simulation according to the standards listed below.
10.1.3 Standards
Table 26. Thermal performance comparison
Thermal
Resistance
1 = Power Chip, 2 = Logic Chip [°C/W]
m = 1,
n = 1
m = 1, n = 2
m
= 2, n = 1
m = 2,
n = 2
R
θJAmn
(1)(2)
27.13 18.31 35.53
R
θJBmn
(2)(3)
14.31 6.54 23.61
R
θJAmn
(1)(4)
47.77 36.90 54.35
R
θJCmn
(5)
1.38 0.00 0.91
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5.
5. Thermal resistance between the die junction and the exposed pad, “infinite” heat sink attached to exposed pad.
24-PIN
PQFN
10XS3435
98ARL10596D
24-PIN PQFN (12 x 12)
Note: For package dimensions, see
98ARL10596D.
T
J1
T
J2
=
R
θJA11
R
θJA21
R
θJA12
R
θJA22
.
P
1
P
2