Datasheet
44 NXP Semiconductors
10XS3435
SO data will represent information ranging from fault status to register contents, user selected by writing to the STATR bits OD4, OD3,
OD2, OD1, and OD0. The value of the previous bits SOA4 and SOA3 will determine which output the SO information applies to for the
registers which are output specific; viz., Fault, PWMR, CONFR0, CONFR1 and OCR registers.
Note that the SO data will continue to reflect the information for each output (depending on the previous SOA4, SOA3 state) that was
selected during the most recent STATR write until changed with an updated STATR write.
The output status register correctly reflects the status of the STATR-selected register data at the time that the CS is pulled to a logic [0]
during SPI communication, and/or for the period of time since the last valid SPI communication, with the following exception:
• The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI
communication never occurred.
• The VPWR voltage is below 4.0 V, the status must be ignored by the MCU.
7.4.4 Serial output bit assignment
The 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 24,
summarizes SO returned data for bits OD15 : OD0.
• Bit OD15 is the MSB; it reflects the state of the Watchdog bit from the previously clocked-in message.
• Bits OD14:OD10 reflect the state of the bits SOA4 : SOA0 from the previously clocked in message.
• Bit OD9 is set to logic [1] in Normal mode (NM).
• The contents of bits OD8 : OD0 depend on bits D4 : D0 from the most recent STATR command SOA4 : SOA0 as explained in the
paragraphs following
Table 24.
7.4.4.1 Previous address SOA4 : SOA0 = A
1
A
0
000 (STATR_S)
The returned data OD8 reports logic [1] in case of previous Power ON Reset condition (V
SUPPLY(POR)
). This bit is only reset by a read
operation.
Bits OD7: OD0 reflect the current state of the Fault register (FLTR) corresponding to the output previously selected with the bits
SOA4:SOA3 = A
1
A
0
(Table 24).
• OC_s: overcurrent fault detection for a selected output,
Table 24. Serial output bit map description
Previous STATR SO Returned Data
SO
A4
SO
A3
SO
A2
SO
A1
SO
A0
OD
15
OD
14
OD
13
OD
12
OD
11
OD
10
OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
STATR_s A
1
A
0
0 0 0 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM POR UV OV OLON_s
OLOFF_
s
OS_s OT_s SC_s OC_s
PWMR_s A
1
A
0
0 0 1 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM 28W_s
ON_s PWM6_s PWM5_s PWM4_s PWM3_s PWM2_s PWM1_s PWM0_s
CONFR0_s A
1
A
0
0 1 0 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM X X X
DIR_dis_
s
SR1_s SR0_s DELAY2_s DELAY1_s DELAY0_s
CONFR1_s A
1
A
0
0 1 1 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM X X
Retry_
unlimited
_s
Retry_dis
_s
OS_dis_s OLON_dis_s OLOFF_dis_s OLLED_en_s
CSNS_ratio_
s
OCR_s A
1
A
0
1 0 0 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM
Xenon
_s
BC1_s
BC0_s OC1_s OC0_s OCHI_s OCLO1_s OCLO0_s OC_mode_s
GCR 0 0 1 0 1 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM
VDD_F
AIL_en
PWM_
en
CLOCK_
sel
TEMP_en
CSNS_e
n
CSNS1 CSNS0 X OV_dis
DIAGR0 0 0 1 1 1 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM X X X X X
X CLOCK_fail
CAL_fail OTW
DIAGR1 0 1 1 1 1 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM X X X X IN3
IN2 IN1
IN0 WD_en
DIAGR2 1 0 1 1 1 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM X X X X X
X 0
1 1
Register state
after
RST = 0
or V
DD(FAIL)
or
V
SUPPLY(POR)
condition
N/A N/A N/A N/A N/A 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 0
s = Output selection with the bits A
1
A
0
as defined in Table 13