Datasheet

NXP Semiconductors 43

10XS3435

7.4.2.6 Address 00101 — Global configuration register (GCR)

The GCR register allows the MCU to configure the device through the SPI.

Bit D8 allows the MCU to enable or disable the VDD failure detector. A logic [1] on VDD_FAIL_en bit allows switch of the outputs HS[0:3]

with PWMR register device in Fail-safe mode in case of V

< V

DD(FAIL).

Bit D7 allows the MCU to enable or disable the PWM module. A logic [1] on PWM_en bit allows control of the outputs HS[0:3] with PWMR

Bit D6 (CLOCK_sel) allows to select the clock used as reference by PWM module, as described in the following Table 21.

Bits D5:D4 allow the MCU to select one of two analog feedback on CSNS output pin, as shown in Table 22.

The GCR register disables the overvoltage protection (D0). When this bits is [0], the overvoltage is enabled (default value).

7.4.2.7 Address 00111 — Calibration register (CALR)

The CALR register allows the MCU to calibrate internal clock, as explained in Figure 16.

7.4.3 Serial output communication (device status return data)

When the CS pin is pulled low, the output register is loaded. Meanwhile, the data is clocked out MSB- (OD15-) first as the new message

data is clocked into the SI pin. The first sixteen bits of data clocking out of the SO, and following a

CS transition, is dependent upon the

previously written SPI word.

Any bits clocked out of the Serial Output (SO) pin after the first 16 bits will be representative of the initial message bits clocked into the SI

pin since the

CS pin first transitioned to a logic [0]. This feature is useful for daisy-chaining devices as well as message verification.

A valid message length is determined following a CS transition of [0] to [1]. If there is a valid message length, the data is latched into the

appropriate registers. A valid message length is a multiple of 16

bits. At this time, the SO pin is tri-stated and the fault status register is

now able to accept new fault status information.

Table 21. PWM module selection

PWM_en (D7) CLOCK_sel (D6) PWM module

0 X PWM module disabled (default)

1 0 PWM module enabled with external clock from IN0

1 1

PWM module enabled with

internal calibrated clock

Table 22. CSNS reporting selection

TEMP_en (D5) CSNS_en (D4) CSNS reporting

0 0 CSNS tri-stated (default)

X 1 current recopy of selected output ([D3:2] bits)

1 0 temperature on GND flag

Table 23. Output current recopy selection

CSNS1 (D3) CSNS0 (D2) CSNS reporting

0 0 HS0 (default)

0 1 HS1

1 0 HS2

1 1 HS3